Patents by Inventor Mark S. Milshtein
Mark S. Milshtein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10651733Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.Type: GrantFiled: July 27, 2015Date of Patent: May 12, 2020Assignee: INTEL CORPORATIONInventors: Gerhard Schrom, Mark S. Milshtein, Alexander Lyakhov
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Publication number: 20150333628Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Applicant: Intel CorporationInventors: Gerhard Schrom, Mark S. Milshtein, Alexander Lyakhov
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Patent number: 9154026Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.Type: GrantFiled: June 27, 2012Date of Patent: October 6, 2015Assignee: Intel CorporationInventors: Gerhard Schrom, Mark S. Milshtein, Alexander Lyakhov
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Publication number: 20140002049Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Inventors: Gerhard Schrom, Mark S. Milshtein, Alexander Lyakhov
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Patent number: 6531897Abstract: A global clock self-timed circuit initiates a precharge pulse in response to which a domino node is precharged. A self-terminating precharge circuit coupled to the global clock self-timed circuit and the domino node terminates the precharge pulse after the domino node has been precharged.Type: GrantFiled: June 30, 2000Date of Patent: March 11, 2003Assignee: Intel CorporationInventors: Mark S. Milshtein, Milo D. Sprague, Terry I. Chappell, Thomas D. Fletcher
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Patent number: 6239621Abstract: A method is provided for precharging a node in an integrated circuit in which the node is precharged a first predetermined delay after the node evaluates and, thereafter, the precharge ceases after a second shorter predetermined delay.Type: GrantFiled: December 29, 1999Date of Patent: May 29, 2001Assignee: Intel CorporationInventors: Mark S. Milshtein, Milo D. Sprague
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Patent number: 6204714Abstract: A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.Type: GrantFiled: September 24, 1998Date of Patent: March 20, 2001Assignee: Intel Corp.Inventors: Mark S. Milshtein, Thomas D. Fletcher, Kevin (Xia) Dai, Terry I. Chappell, Milo D. Sprague
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Patent number: 6023182Abstract: A pulse generating circuit includes a first pulse generating circuit for generating a first output pulse, and a second pulse generating circuit for outputting a second output pulse. Each pulse generating circuit comprises a stack of two n-channel transistors and a reset circuit. The reset circuit includes two p-channel transistors and two inverters and is provided for automatically resetting the pulse generating circuits. The second pulse generating circuit includes a delay element for introducing an additional gate delay in the generation of the second output pulse. The additional gate delay introduces an asymmetry in the output pulses which offsets or cancels a previously introduced asymmetry of an input clock signal to generate an output clock signal having a constant period. Clock gating circuitry is provided for selectively enabling and disabling at least one of said pulse generator circuits.Type: GrantFiled: December 31, 1997Date of Patent: February 8, 2000Assignee: Intel CorporationInventors: Mark S. Milshtein, Thomas D. Fletcher, Terry Chappell
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Patent number: 5942917Abstract: A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.Type: GrantFiled: December 29, 1997Date of Patent: August 24, 1999Assignee: Intel CorporationInventors: Barbara A. Chappell, Terry I. Chappell, Mark S. Milshtein, Thomas D. Fletcher
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Patent number: 5162891Abstract: A lateral injection group III-V heterostructure device having self-aligned graded contact diffusion regions of opposite conductivity types and a method of fabricating such devices are disclosed. The device includes a heterojunction formed by a higher bandgap III-V compound semiconductor formed over a lower bandgap III-V compound semiconductor. The method of the present invention allows the opposite conductivity type diffusion regions to diffuse simultaneously and penetrate the heterojunction. This results in compositional mixing of the compound semiconductor materials forming the heterojunction in the diffusion regions.Type: GrantFiled: July 3, 1991Date of Patent: November 10, 1992Assignee: International Business Machines CorporationInventors: Jeremy H. Burroughes, Mark S. Milshtein, Michael A. Tischler, Sandip Tiwari, Steven L. Wright
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Patent number: 5158896Abstract: A lateral injection group III-V heterostructure device having self-aligned graded contact diffusion regions of opposite conductivity types and a method of fabricating such devices are disclosed. The device includes a heterojunction formed by a higher bandgap III-V compound semiconductor formed over a lower bandgap III-V compound semiconductor. The method of the present invention allows the opposite conductivity type diffusion regions to diffuse simultaneously and penetrate the heterojunction. This results in compositional mixing of the compound semiconductor materials forming the heterojunction in the diffusion regions.Type: GrantFiled: January 9, 1992Date of Patent: October 27, 1992Assignee: International Business Machines CorporationInventors: Jeremy H. Burroughes, Mark S. Milshtein, Michael A. Tischler, Sandip Tiwari, Steven L. Wright