Patents by Inventor Mark S. Moir

Mark S. Moir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170236120
    Abstract: Distributed ledger systems that provide enhanced accountability and trust are described. A sender node may send messages to a receiver node. The sender node may compute a value (e.g., a hash) based on the sent messages and at least one previously sent message. The sender node may receive a confirmation message for the messages from the receiver node including a value computed by the receiver node based on the messages and at least one previously received message. The sender node may compare the computed value to the value included in the confirmation message to determine that the receiver node has or has not received a correct sequence of messages. The confirmation message may also include a summary of local data of the receiver node that indicates to the sender node that the receiver node has or has not processed all messages received.
    Type: Application
    Filed: May 31, 2016
    Publication date: August 17, 2017
    Inventors: Maurice P. Herlihy, Mark S. Moir
  • Patent number: 9727369
    Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: August 8, 2017
    Assignee: Oracle International Corporation
    Inventors: David Dice, Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir
  • Patent number: 9619281
    Abstract: Particular techniques for improving the scalability of concurrent programs (e.g., lock-based applications) may be effective in some environments and for some workloads, but not others. The systems described herein may automatically choose appropriate ones of these techniques to apply when executing lock-based applications at runtime, based on observations of the application in the current environment and with the current workload. In one example, two techniques for improving lock scalability (e.g., transactional lock elision using hardware transactional memory, and optimistic software techniques) may be integrated together. A lightweight runtime library built for this purpose may adapt its approach to managing concurrency by dynamically selecting one or more of these techniques (at different times) during execution of a given application.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: April 11, 2017
    Assignee: Oracle International Corporation
    Inventors: David Dice, Alex Kogan, Yosef Lev, Timothy M. Merrifield, Mark S. Moir
  • Publication number: 20160259663
    Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Inventors: David Dice, Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir
  • Patent number: 9417910
    Abstract: The systems and methods described herein may implement probabilistic counters and/or update mechanisms for those counters such that they are dependent on the value of a configurable accuracy parameter. The accuracy parameter value may be adjusted to provide fine-grained control over the tradeoff between the accuracy of the counters and the performance of applications that access them. The counters may be implemented as data structures that include a mantissa portion and an exponent portion that collectively represent an update probability value. When updating the counters, the value of the configurable accuracy parameter may affect whether, when, how often, or by what amount the mantissa portion and/or the exponent portion are updated. Updating a probabilistic counter may include multiplying its value by a constant that is dependent on the value of a configurable accuracy parameter. The counters may be accessible within transactions. The counters may have deterministic update policies.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 16, 2016
    Assignee: Oracle International Corporation
    Inventors: David Dice, Yosef Lev, Mark S. Moir
  • Publication number: 20160216966
    Abstract: A computer system may recognize a busy-wait loop in program instructions at compile time and/or may recognize busy-wait looping behavior during execution of program instructions. The system may recognize that an exit condition for a busy-wait loop is specified by a conditional branch type instruction in the program instructions. In response to identifying the loop and the conditional branch type instruction that specifies its exit condition, the system may influence or override a prediction made by a dynamic branch predictor, resulting in a prediction that the exit condition will be met and that the loop will be exited regardless of any observed branch behavior for the conditional branch type instruction. The looping instructions may implement waiting for an inter-thread communication event to occur or for a lock to become available. When the exit condition is met, the loop may be exited without incurring a misprediction delay.
    Type: Application
    Filed: April 4, 2016
    Publication date: July 28, 2016
    Inventors: David Dice, Mark S. Moir
  • Patent number: 9367363
    Abstract: Systems and methods for integrating multiple best effort hardware transactional support mechanisms, such as Read Set Monitoring (RSM) and Best Effort Hardware Transactional Memory (BEHTM), in a single transactional memory implementation are described. The best effort mechanisms may be integrated such that the overhead associated with support of multiple mechanisms may be reduced and/or the performance of the resulting transactional memory implementations may be improved over those that include any one of the mechanisms, or an un-integrated collection of multiple such mechanisms. Two or more of the mechanisms may be employed concurrently or serially in a single attempt to execute a transaction, without aborting or retrying the transaction. State maintained or used by a first mechanism may be shared with or transferred to another mechanism for use in execution of the transaction. This transfer may be performed automatically by the integrated mechanisms (e.g., without user, programmer, or software intervention).
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: June 14, 2016
    Assignee: Oracle America, Inc.
    Inventors: Mark S. Moir, David Dice
  • Patent number: 9342380
    Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 17, 2016
    Assignee: Oracle International Corporation
    Inventors: David Dice, Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir
  • Patent number: 9323586
    Abstract: We teach a powerful approach that greatly simplifies the design of non-blocking mechanisms and data structures, in part by, largely separate the issues of correctness and progress. At a high level, our methodology includes designing an “obstruction-free” implementation of the desired mechanism or data structure, which may then be combined with a contention management mechanism whose role is to facilitate the conditions under which progress of the obstruction-free implementation is assured. In general, the contention management mechanism is separable semantically from an obstruction-free concurrent shared/sharable object implementation to which it is/may be applied. In some cases, the contention management mechanism may actually be coded separately from the obstruction-free implementation. We elaborate herein on the notions of obstruction-freedom and contention management, and various possibilities for combining the two.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: April 26, 2016
    Assignee: Oracle International Corporation
    Inventors: Mark S. Moir, Victor M. Luchangco, Maurice Herlihy
  • Patent number: 9304776
    Abstract: A computer system may recognize a busy-wait loop in program instructions at compile time and/or may recognize busy-wait looping behavior during execution of program instructions. The system may recognize that an exit condition for a busy-wait loop is specified by a conditional branch type instruction in the program instructions. In response to identifying the loop and the conditional branch type instruction that specifies its exit condition, the system may influence or override a prediction made by a dynamic branch predictor, resulting in a prediction that the exit condition will be met and that the loop will be exited regardless of any observed branch behavior for the conditional branch type instruction. The looping instructions may implement waiting for an inter-thread communication event to occur or for a lock to become available. When the exit condition is met, the loop may be exited without incurring a misprediction delay.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 5, 2016
    Assignee: Oracle International Corporation
    Inventors: David Dice, Mark S. Moir
  • Publication number: 20160062796
    Abstract: Particular techniques for improving the scalability of concurrent programs (e.g., lock-based applications) may be effective in some environments and for some workloads, but not others. The systems described herein may automatically choose appropriate ones of these techniques to apply when executing lock-based applications at runtime, based on observations of the application in the current environment and with the current workload. In one example, two techniques for improving lock scalability (e.g., transactional lock elision using hardware transactional memory, and optimistic software techniques) may be integrated together. A lightweight runtime library built for this purpose may adapt its approach to managing concurrency by dynamically selecting one or more of these techniques (at different times) during execution of a given application.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: David Dice, Alex Kogan, Yosef Lev, Timothy M. Merrifield, Mark S. Moir
  • Publication number: 20160011915
    Abstract: Transactional Lock Elision allows hardware transactions to execute unmodified critical sections protected by the same lock concurrently, by subscribing to the lock and verifying that it is available before committing the transaction. A “lazy subscription” optimization, which delays lock subscription, can potentially cause behavior that cannot occur when the critical sections are executed under the lock. Hardware extensions may provide mechanisms to ensure that lazy subscriptions are safe (e.g., that they result in correct behavior). Prior to executing a critical section transactionally, its lock and subscription code may be identified (e.g., by writing their locations to special registers). Prior to committing the transaction, the thread executing the critical section may verify that the correct lock was correctly subscribed to. If not, or if locations identified by the special registers have been modified, the transaction may be aborted.
    Type: Application
    Filed: June 10, 2015
    Publication date: January 14, 2016
    Inventors: David Dice, Timothy L. Harris, Alex Kogan, Yosef Lev, Mark S. Moir
  • Patent number: 9208081
    Abstract: A processing thread obtains an initial status of a reference field associated with an object having data stored in memory. The reference field represents, at least in part, a status of current modification operations (e.g., a status of moving the object from one location in memory to another), if any, applied to the object. The processing thread applies a sequence of instructions to data retrieved from the object to produce computational results for storage in the object. Prior to storing the computational results in the object, the processing thread can confirm whether the reference field has changed since obtaining the initial status.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: December 8, 2015
    Assignee: Oracle America, Inc.
    Inventors: David Dice, Nir N. Shavit, Mark S. Moir, Antonios Printezis
  • Patent number: 9183048
    Abstract: The systems and methods described herein may implement scalable statistics counters that are adaptive to the amount of contention for the counters. The counters may be accessible within transactions. Methods for determining whether or when to increment the counters in response to initiation of an increment operation and/or methods for updating the counters may be selected dependent on current, recent, or historical amounts of contention. Various contention management policies or retry conditions may be applied to select between multiple methods. One counter may include a precise counter portion that is incremented under low contention and a probabilistic counter portion that is updated under high contention. Amounts by which probabilistic counters are incremented may be contention-dependent. Another counter may include a node identifier portion that encourages consecutive increments by threads on a single node only when under contention.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Oracle International Corporation
    Inventors: David Dice, Yosef Lev, Mark S. Moir
  • Patent number: 9183043
    Abstract: Particular techniques for improving the scalability of concurrent programs (e.g., lock-based applications) may be effective in some environments and for some workloads, but not others. The systems described herein may automatically choose appropriate ones of these techniques to apply when executing lock-based applications at runtime, based on observations of the application in the current environment and with the current workload. In one example, two techniques for improving lock scalability (e.g., transactional lock elision using hardware transactional memory, and optimistic software techniques) may be integrated together. A lightweight runtime library built for this purpose may adapt its approach to managing concurrency by dynamically selecting one or more of these techniques (at different times) during execution of a given application.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 10, 2015
    Assignee: Oracle International Corporation
    Inventors: David Dice, Alex Kogan, Yosef Lev, Timothy M. Merrifield, Mark S. Moir
  • Publication number: 20150269008
    Abstract: We teach a powerful approach that greatly simplifies the design of non-blocking mechanisms and data structures, in part by, largely separate the issues of correctness and progress. At a high level, our methodology includes designing an “obstruction-free” implementation of the desired mechanism or data structure, which may then be combined with a contention management mechanism whose role is to facilitate the conditions under which progress of the obstruction-free implementation is assured. In general, the contention management mechanism is separable semantically from an obstruction-free concurrent shared/sharable object implementation to which it is/may be applied. In some cases, the contention management mechanism may actually be coded separately from the obstruction-free implementation. We elaborate herein on the notions of obstruction-freedom and contention management, and various possibilities for combining the two.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventors: Mark S. Moir, Victor M. Luchangco, Maurice Herlihy
  • Patent number: 9135178
    Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 15, 2015
    Assignee: Oracle International Corporation
    Inventors: Nir N. Shavit, Mark S. Moir, Victor M. Luchangco
  • Publication number: 20150248310
    Abstract: In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.
    Type: Application
    Filed: April 27, 2015
    Publication date: September 3, 2015
    Inventors: David Dice, Mark S. Moir
  • Patent number: 9110718
    Abstract: The present embodiments provide a system for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor in the shared-memory multiprocessor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. The system includes an interface, such as an application programming interface (API), and a system call interface or an instruction-set architecture (ISA) that provides access to a number of mechanisms for supporting targeted stores. These mechanisms include a thread-location mechanism that determines a location near where a thread is executing in the shared-memory multiprocessor, and a targeted-store mechanism that targets a store to a location (e.g., cache memory) in the shared-memory multiprocessor.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: August 18, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mark S. Moir, David Dice, Paul N. Loewenstein
  • Patent number: 9052944
    Abstract: We teach a powerful approach that greatly simplifies the design of non-blocking mechanisms and data structures, in part by, largely separate the issues of correctness and progress. At a high level, our methodology includes designing an “obstruction-free” implementation of the desired mechanism or data structure, which may then be combined with a contention management mechanism whose role is to facilitate the conditions under which progress of the obstruction-free implementation is assured. In general, the contention management mechanism is separable semantically from an obstruction-free concurrent shared/sharable object implementation to which it is/may be applied. In some cases, the contention management mechanism may actually be coded separately from the obstruction-free implementation. We elaborate herein on the notions of obstruction-freedom and contention management, and various possibilities for combining the two.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: June 9, 2015
    Assignee: Oracle America, Inc.
    Inventors: Mark S. Moir, Victor M. Luchangco, Maurice Herlihy