Abstract: A system for drying structures including an enclosed housing with a plurality of outlet openings, a plurality of flexible outlet hoses each connected to a respective outlet opening, and a vacuum motor engaged with the housing such that an outlet of the vacuum motor is exhausted into an interior of the housing so as to pressurize the interior of the housing such that compressed air is directed through the plurality of outlet hoses. Also a method of drying an interior of a structure, including placing a pressurized drying system adjacent a region of a structure, forming a plurality of openings in surfaces of the structure where the surfaces define enclosed spaces, inserting distal ends of outlet hoses of the pressurized drying system into respective openings of the surfaces of the structure, and engaging the pressurized drying system so as to generate a flow of pressurized air and to direct the pressurized air into the enclosed spaces.

Abstract: A highly reliable computer memory storage system that is divided into subsystems, each of which is provided in triplicate: a primary subsystem, a backup subsystem and a spare subsystem. Upon detection of a non-recoverable failure in a primary subsystem, the backup subsystem substantially immediately assumes the tasks of the primary subsystem while the spare subsystem is integrated into the operation of the computer memory storage system. The triple replication of all subsystems and mechanisms for detecting failures in at least the primary and secondary subsystems provides an overall memory system which is highly reliable and substantially never requires servicing. In an alternative embodiment, three subsystems can share a load equally, for example a cooling or power supply load requirement.

Abstract: A highly reliable computer memory storage system that is divided into subsystems, each of which is provided in triplicate: a primary subsystem, a backup subsystem and a spare subsystem. Upon detection of a non-recoverable failure in a primary subsystem, the backup subsystem substantially immediately assumes the tasks of the primary subsystem while the spare subsystem is integrated into the operation of the computer memory storage system. The triple replication of all subsystems and mechanisms for detecting failures in at least the primary and secondary subsystems provides an overall memory system which is highly reliable and substantially never requires servicing. In an alternative embodiment, three subsystems can share a load equally, for example a cooling or power supply load requirement.

Abstract: A system and method for ensuring the completion and integrity of data modification operations to a redundant array data storage system and for ensuring the integrity of redundancy values in such a system.

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ("DMA"), and a processor support module ("PSM"); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the tru-complement pair of microprocessors to operate in lockstep.

Abstract: A digital logic circuit and method for synchronizing the leading edges skewed true-complement signal pair. The circuit is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines.