Abstract: The topology of a network is represented, or emulated, by a topology engine comprising processing elements interconnected via a connection matrix. Queries representing physical problems of the network are supplied by a host processor to the topology engine, where they are processed in the processing elements in accordance with the topology to produce responses which are returned to the host processor. In particular, the network can be a communications network and the queries can comprise search requests for determining connection paths between devices of the network. The topology engine can use processors with multiple instances so that it is more compact than the communications network that it represents.

Abstract: The present invention provides a method and apparatus for establishing dedicated local area network (LAN) connectivity between network elements (NEs) in an optical transmission network without using any of the payload transport capacity available. In order to provision dedicated LAN connections between NEs, the invention reallocates existing overhead functionality to provide dedicated bandwidth for LAN communications between NEs. At each NE, a respective LAN interface unit provides access to this dedicated bandwidth and allows LAN devices such as personal computers (PCs), servers and monitoring equipment to communicate across NEs of an optical transmission network without consuming any payload transport capacity available therein.

Abstract: A peak detector for measuring the voltage amplitude of low amplitude balanced digital signals. The N-diode peak detector uses the non-linear characteristics of a diode to convert a high speed low amplitude input signal into a DC voltage, linearly proportional to the signal amplitude (peak). A compensation circuit is designed to match the characteristics of a digital modulation signal and track over a large range of temperatures and signal amplitudes. The circuit can be used for digital and analog modulation signals. For analog signals, the peak detector uses a larger number of diodes or a reduced range.

Abstract: A gain control amplifier includes an input differential circuit having a pair of transistors, the emitters of which are coupled via a pair of emitter resistors. The input differential circuit includes a current sink for providing an operating current. With variation of the operating current, the gain control amplifier's gain is varied. Two emitter coupled differential amplifiers are connected to the input differential circuit having a current sink. A current flowing in the transistors of the emitter coupled differential amplifier and the input differential circuit is split by an additional emitter coupled differential circuit having a current sink. A current splitting factor is controlled in response to the voltage difference between the collectors of the two transistors of the two emitter coupled differential amplifiers. Since the relatively small currents flow in the emitter resistors, noise caused thereby is relatively low. Thus, it provides a wide input dynamic range with low noise.

Abstract: A receiver for Manchester encoded data includes an autocalibration feedback loop that generates a timing pulse used to recover the clock and data signals. The autocalibration feedback loop includes a first digital delay line sampled by a plurality of D-type flip-flops in dependence upon the recovered clock signal to produce a control word CNT(O:N) indicative of the number of digital delay elements required to approximate one-half of the recovered clock period. A second digital delay line, connectivity mapped to the first, provides three-eights of a clock period delay. The delayed clock signal is derived from the bit stream by sampling in dependence upon the timing pulse. The decoded data signal is derived from the bit stream by multiplexing the sampling input in dependence upon the timing pulse and the decoded data signal.

Abstract: A phase error integrator for determining the phase error between a data signal and a clock signal frequency locked to the data signal has a data input and a clock input. In one embodiment the phase error integrator is formed as two functional components, namely a phase error detector and an integrator chain. The phase error detector sends to the integrator one of two output signals depending on whether the phase error is positive or negative. The integrator chain has a number of outputs the first half of which initially have a binary 1 and the second half of which initially have a binary 0. Depending on which output signal arrives from the phase error detector the binary 1's shift right or the binary 0's shift left. The integrator may be combined with a delay block connected to the outputs of the integrator chain. The data signal is fed to the delay block and delayed data output signal is obtained which is connected to the data input of the phase error integrator.

Abstract: A decoder for Manchester encoded data includes an up/down counter which constitutes a state machine. Consecutive bits with the same binary value in the encoded data bit stream enable the counter, whic is incremented or decremented in dependence upon the relative phase of an output clock signal. Incrementing occurs in response to phase errors of the output clock signal, and decrementing to a count of zero occurs in response to phase assertions indicating a correct phase of the clock signal. The phase of the clock signal is reversed, and the counter reset, if a maximum count is reached in response to repeated phase errors. Such a phase reversal or phase slip is avoided in the presence of single bit errors in the bit stream. The decoded data is derived from the bit stream by sampling in dependence upon the clock signal.

Abstract: A method of and apparatus for synchronizing an asynchronous DS1 signal to produce a synchronized signal in the SONET format is described. The asynchronous signal is stuffed in dependence upon a stuff request signal which is produced from a comparison with a threshold level of a phase difference between read and write phases with which the synchronized and asynchronous signals are respectively read from and written into an elastic store. The phase detection and threshold comparison are effected synchronously with the respective signals. To this end, the read address for the store is latched in synchronism with the synchronized frames, and its difference from the write address and the resulting threshold level comparison is effected in synchronism with the write clock for the store and hence with the asynchronous signal. The synchronizer provides a reduced waiting time jitter in the synchronized signal.

Abstract: The invention provides an interface circuit for connection between an input data port and a data receiver. A data recovery circuit is responsive to a data stream on the input port for generating data pulses corresponding thereto and a clock recovery circuit is responsive to the data pulses for generating clock signals. A circuit is responsive to the clock signals and the data pulses for generating, for each data pulse, a recognition window having a maximum width approximately corresponding to the combined duration of the data pulse being recognized and one of the clock pulses. A data synchronization circuit is responsive to the output from the circuit and to the recovered clock signals for generating synchronous data.