Abstract: A dynamic incrementer, implemented in the Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS) circuit family, which internally performs single rail calculations and which generates the dual rail result using a strobing technique. The carry-lookahead function is implemented with an OR tree using the complement input signals, resulting in a very fast and economical incrementer.

Abstract: A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode.

Abstract: An automatic and adaptive threshold setting circuit for an IR receiver is capable of operating over a broad range of frequencies and power levels. The adaptive threshold circuit allows a very sensitive threshold in environments where little sunlight or other ambient light reaches the receiver, but which will increase the threshold of the receiver when large amounts of ambient light fall on the photo diode. The circuit senses the current flowing through the reverse biased IR photo detector due to ambient light levels. This current measurement is used to adjust the sensitivity of the receiver.