Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: The present invention is directed to a system, method, and apparatus to transmit/receive TMDS signals using general purpose differential transmitter and receivers. In an embodiment, the general purpose differential transmitter and receivers are designed to operate with differential signaling schemes such as LVDS and LVPECL. In one aspect, embodiments according to the present invention enable the re-configuration of existing and fully-characterized LVDS/LVPECL transmitter/receiver cells to support TMDS (using minimal sets of external components). This provides considerable cost and development time savings, thereby allowing the development of products much more expediently. In another aspect, embodiments according to the present invention provide interfacing methods and systems between differential signaling schemes such as LVDS/LVPECL and TMDS.

Abstract: A improved method and system for regenerating a video pixel and/or audio sampling clock in a system that wirelessly transfers video and audio content from a content source to a content sink.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: A method and apparatus for receiving and transmitting network frames via an internetworking device, in which a first portion of a total number of buffers is allocated among port-dedicated buffer pools, and a second portion is placed in a common pool accessible by any of the network ports. A frame is received at a first port, and a list of buffers accessible only by that port is referenced to identify buffers not already in use. A second list of buffers in the common pool is referenced to identify unused buffers for use if insufficient unused buffer space is available in the port-dedicated buffer pool. Frame data is then stored in the identified buffer(s). Upon retransmission, the buffer(s) used to store the. transmitted frame is released to the port-dedicated and/or common buffer pool(s).

Abstract: A method and apparatus for receiving and transmitting network frames via an internetworking device, in which a first portion of a total number of buffers is allocated among port-dedicated buffer pools, and a second portion is placed in a common pool accessible by any of the network ports. A frame is received at a first port, and a list of buffers accessible only by that port is referenced to identify buffers not already in use. A second list of buffers in the common pool is referenced to identify unused buffers for use if insufficient unused buffer space is available in the port-dedicated buffer pool. Frame data is then stored in the identified buffer(s). Upon retransmission, the buffer(s) used to store the transmitted frame is released to the port-dedicated and/or common buffer pool(s).

Abstract: A magnetic tape drive emulator provides interface compatibility between a computer system having an industry standard tape drive interface and a peripheral image acquisition processing system. The emulator receives signals that are normally applied to a magnetic tape drive system and converts them into data signals which are formatted for general access by the image acquisition processing system. In addition, the magnetic tape drive emulator converts signals generated by the peripheral processing system into data signals which are formatted for access by the computer system through the standard tape drive interface.

Abstract: A electro-mechanical device for measuring the angle made by two rotatably joined members comprising a pair of rotatably connected elongated arms and electrical circuit means mounted on one of the arms and associated with the rotatable pin connector of the arms. The circuit, powered by a battery, encodes the angle of the pin preferably via a potentiometer and transmits the information to a decoding device, preferably a voltmeter, and then to a digital display device also mounted on one of the arms.