Patents by Inventor Mark Shlick
Mark Shlick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240355400Abstract: To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.Type: ApplicationFiled: July 3, 2023Publication date: October 24, 2024Applicant: SanDisk Technologies LLCInventors: Abu Naser Zainuddin, Mark Shlick, Jiahui Yuan
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Publication number: 20240257878Abstract: An apparatus is provided that includes a plurality of non-volatile memory cells, a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells, and a control circuit coupled to the non-volatile memory cells and the charge pump circuit. The control circuit is configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal depending on a memory operation being performed on the non-volatile memory cells.Type: ApplicationFiled: July 19, 2023Publication date: August 1, 2024Applicant: SanDisk Technologies LLCInventors: Abu Naser Zainuddin, Jiahui Yuan, Mark Shlick, Shemmer Choresh
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Patent number: 11449236Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.Type: GrantFiled: May 1, 2020Date of Patent: September 20, 2022Assignee: Western Digital Technologies, Inc.Inventors: David Avraham, Omer Fainzilber, Mark Shlick, Yoav Markus
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Patent number: 11409443Abstract: A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.Type: GrantFiled: February 17, 2021Date of Patent: August 9, 2022Assignee: Western Digital Technologies, Inc.Inventors: Ravi Kumar, Deepanshu Dutta, Niles Yang, Mark Shlick
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Patent number: 11385802Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.Type: GrantFiled: March 27, 2020Date of Patent: July 12, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Eran Sharon, Nian Niles Yang, Idan Alrod, Evgeny Mekhanik, Mark Shlick, Joanna Lai
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Patent number: 11373710Abstract: Time division peak power management in non-volatile memory systems is disclosed. The memory system has a memory controller and a number of semiconductor dies. Each die is assigned a time slot in which to perform high current portions of memory operations. The memory controller provides an external clock to each die. Each die tracks repeating time slots based on the external clock. The memory controller may synchronize this tracking. If a die is about to perform a high current portion of a memory operation, the die checks to determine if its allocated slot has been reached. If not, the die halts the memory operation until its allocated time slot is reached. When the allocated time slot is reached, the halted memory operation is resumed at the high current portion. Therefore, the high current portion of the memory operation occurs during the allocated time slot.Type: GrantFiled: February 2, 2021Date of Patent: June 28, 2022Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, Yu-Chung Lien, Mark Murin, Mark Shlick
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Publication number: 20220171541Abstract: A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.Type: ApplicationFiled: February 17, 2021Publication date: June 2, 2022Inventors: Ravi Kumar, Deepanshu Dutta, Niles Yang, Mark Shlick
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Publication number: 20210342095Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.Type: ApplicationFiled: May 1, 2020Publication date: November 4, 2021Inventors: David Avraham, Omer Fainzilber, Mark Shlick, Yoav Markus
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Publication number: 20200225852Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Eran SHARON, Nian Niles YANG, Idan ALROD, Evgeny MEKHANIK, Mark SHLICK, Joanna LAI
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Patent number: 10642510Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.Type: GrantFiled: June 7, 2018Date of Patent: May 5, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Eran Sharon, Nian Niles Yang, Idan Alrod, Evgeny Mekhanik, Mark Shlick, Joanna Lai
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Patent number: 10580495Abstract: Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a memory module comprising non-volatile memory. Here, the memory module is configured to program a page of non-volatile memory with a first number of program cycles and indicate (e.g., to a host) that the page is partially programmed. The memory module is also configured to program the page with a second number of program cycles after a predetermined time, wherein the memory module performs one or more other storage operations during the predetermined time, and indicate (e.g., to the host) that the page is fully programmed.Type: GrantFiled: December 21, 2017Date of Patent: March 3, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Refael Ben-Rubi, Mark Shlick
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Patent number: 10481816Abstract: Apparatus, systems, methods, and computer program products for providing dynamically assignable data latches are disclosed. A non-volatile memory die includes a non-volatile memory medium. A plurality of sets of data latches of a non-volatile memory die are configured to facilitate transmission of data to and from a non-volatile memory medium, and each of the sets of data latches are associated with a different identifier. An on-die controller is in communication with a sets of data latches. An on-die controller is configured to receive a first command for a first memory operation comprising a selected identifier. An on-die controller is configured to execute a first memory operation on a non-volatile memory medium using a set of data latches of a plurality of sets of data latches, and the set of data latches is associated with a selected identifier.Type: GrantFiled: October 18, 2017Date of Patent: November 19, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mark Shlick, Hadas Oshinsky, Amir Shaharabany, Yoav Markus
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Patent number: 10360045Abstract: A device or apparatus may be configured to perform memory operations on a memory die while a current multi-level cell programming operation is being performed. In the event that a controller identifies pending memory operations to be performed in the memory die, the controller may communicate with the memory die to determine a status of auxiliary latches of the memory die. Depending on the status, the controller may determine if the memory die is in a suspend/resume period and/or which pending memory operations to have performed.Type: GrantFiled: April 25, 2017Date of Patent: July 23, 2019Assignee: SanDisk Technologies LLCInventors: Uri Peltz, Amir Hadar, Mark Shlick, Mark Murin
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Publication number: 20190198113Abstract: Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a memory module comprising non-volatile memory. Here, the memory module is configured to program a page of non-volatile memory with a first number of program cycles and indicate (e.g., to a host) that the page is partially programmed. The memory module is also configured to program the page with a second number of program cycles after a predetermined time, wherein the memory module performs one or more other storage operations during the predetermined time, and indicate (e.g., to the host) that the page is fully programmed.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Applicant: Western Digital Technologies, Inc.Inventors: REFAEL BEN-RUBI, MARK SHLICK
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Publication number: 20190114103Abstract: Apparatus, systems, methods, and computer program products for providing dynamically assignable data latches are disclosed. A non-volatile memory die includes a non-volatile memory medium. A plurality of sets of data latches of a non-volatile memory die are configured to facilitate transmission of data to and from a non-volatile memory medium, and each of the sets of data latches are associated with a different identifier. An on-die controller is in communication with a sets of data latches. An on-die controller is configured to receive a first command for a first memory operation comprising a selected identifier. An on-die controller is configured to execute a first memory operation on a non-volatile memory medium using a set of data latches of a plurality of sets of data latches, and the set of data latches is associated with a selected identifier.Type: ApplicationFiled: October 18, 2017Publication date: April 18, 2019Applicant: Western Digital Technologies, Inc.Inventors: MARK SHLICK, HADAS OSHINSKY, AMIR SHAHARABANY, YOAV MARKUS
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Patent number: 10162538Abstract: A data storage device includes a controller and a memory. The memory is coupled to the controller. The memory includes storage elements coupled to bit lines. The controller is configured to access bit line integrity data corresponding to a region of the memory, the bit line integrity data indicating a number of bit lines. The controller is also configured to store data related to a memory operation threshold based on the number of bit lines.Type: GrantFiled: September 30, 2015Date of Patent: December 25, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Mark Shlick, Refael Ben-Rubi, Uri Shir, Ahiad Turgeman, Uri Peltz
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Publication number: 20180307503Abstract: A device or apparatus may be configured to perform memory operations on a memory die while a current multi-level cell programming operation is being performed. In the event that a controller identifies pending memory operations to be performed in the memory die, the controller may communicate with the memory die to determine a status of auxiliary latches of the memory die. Depending on the status, the controller may determine if the memory die is in a suspend/resume period and/or which pending memory operations to have performed.Type: ApplicationFiled: April 25, 2017Publication date: October 25, 2018Applicant: SanDisk Technologies LLCInventors: Uri Peltz, Amir Hadar, Mark Shlick, Mark Murin
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Publication number: 20180293009Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.Type: ApplicationFiled: June 7, 2018Publication date: October 11, 2018Inventors: Eran SHARON, Nian Niles YANG, Idan ALROD, Evgeny MEKHANIK, Mark SHLICK, Joanna LAI
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Patent number: 9996281Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.Type: GrantFiled: May 27, 2016Date of Patent: June 12, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Eran Sharon, Nian Niles Yang, Idan Alrod, Evgeny Mekhanik, Mark Shlick, Joanna Lai
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Publication number: 20170255403Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.Type: ApplicationFiled: May 27, 2016Publication date: September 7, 2017Inventors: ERAN SHARON, NIAN NILES YANG, IDAN ALROD, EVGENY MEKHANIK, MARK SHLICK, JOANNA LAI