Abstract: A frequency reference generator includes (i) an integrated frequency source having drive circuitry that drives a resonant (e.g., non-trimmable LC) tank to generate an oscillator signal, (ii) at least one temperature sensor that generates at least one measured temperature signal, and (iii) a frequency-adjustment circuit that adjusts the oscillator signal frequency to generate the frequency reference based on the measured temperature signal and a (e.g., sample-specific) mapping from temperature to a corresponding frequency-adjustment parameter (e.g., a divisor value for a fractional frequency divider). In some embodiments, a Colpitts oscillator generates the oscillator signal based on the measured temperature signal, where the Colpitts oscillator has voltage/temperature-compensation circuitry that compensates for variations in power supply voltage and operating temperature. Such frequency reference generators achieve substantial PVT insensitivity with as little as a single 1T-trim or even no trim at all.

Abstract: An electronic circuit is disclosed for dividing the frequency of a periodic signal, wherein at least one of the memory elements is arranged with its output terminal connected to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals. Each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal. At least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.

Abstract: An electronic circuit is disclosed for dividing the frequency of a periodic signal, wherein at least one of the memory elements is arranged with its output terminal connected to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals. Each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal. At least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.