Abstract: Methods and systems of operating a computer system including a processor are disclosed. In one aspect, a method includes providing a discretized operating system for controlling applications executed by the computer system, and replacing an idle task of the discretized operating system with a substitute idle task that causes the processor to enter a dormant mode, a priority level of the substitute idle task being the same as a priority level of the idle task.

Abstract: Methods and systems of operating a computer system including a processor are disclosed. In one aspect, a method includes providing a discretized operating system for controlling applications executed by the computer system, and replacing an idle task of the discretized operating system with a substitute idle task that causes the processor to enter a dormant mode, a priority level of the substitute idle task being the same as a priority level of the idle task.

Abstract: A method for reducing power consumption and heat generation in a computer system employs a substitute idle task that puts the processor into a dormant mode, e.g., sleep, nap, or doze mode. The substitute idle task replaces a conventional operating system idle task. The substitute idle task may have a low priority, such as that of the conventional idle task, which it replaces. At each occurrence of a quantum interrupt, a task scheduler schedules applications for execution during the accompanying time slice. After the scheduled applications are done, the substitute idle task is executed. The dormant mode caused by the idle task reduces the system's power consumption. The idle task may also have a high priority and be designed to run for a predetermined percentage of time. As the processor spends the predetermined percentage of time in the dormant mode, known power consumption reduction may be guaranteed in the system.

Abstract: A method for reducing power consumption and heat generation in a computer system employs a substitute idle task that puts the processor into a dormant mode, e.g., sleep, nap, or doze mode. The substitute idle task replaces a conventional operating system idle task. The substitute idle task may have a low priority, such as that of the conventional idle task, which it replaces. At each occurrence of a quantum interrupt, a task scheduler schedules applications for execution during the accompanying time slice. After the scheduled applications are done, the substitute idle task is executed. The dormant mode caused by the idle task reduces the system's power consumption. The idle task may also have a high priority and be designed to run for a predetermined percentage of time. Because the processor spends the predetermined percentage of time in the dormant mode, known power consumption reduction may be guaranteed in the system.

Abstract: A method for reducing power consumption and heat generation in a computer system employs a substitute idle task that puts the processor into a dormant mode, e.g., sleep, nap, or doze mode. The substitute idle task replaces a conventional operating system idle task. The substitute idle task may have a low priority, such as that of the conventional idle task, which it replaces. At each occurrence of a quantum interrupt, a task scheduler schedules applications for execution during the accompanying time slice. After the scheduled applications are done, the substitute idle task is executed. The dormant mode caused by the idle task reduces the system's power consumption. The idle task may also have a high priority and be designed to run for a predetermined percentage of time. As the processor spends the predetermined percentage of time in the dormant mode, known power consumption reduction may be guaranteed in the system.

Abstract: The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached.

Abstract: A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.

Abstract: The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached.

Abstract: The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached.

Abstract: A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.

Abstract: A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.

Abstract: The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached.