Patents by Inventor Mark Steven Farrell
Mark Steven Farrell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6125444Abstract: A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.Type: GrantFiled: April 30, 1998Date of Patent: September 26, 2000Assignee: International Business Machines CorporationInventors: Mark Anthony Check, John Stephen Liptay, Timothy John Slegel, Charles Franklin Webb, Mark Steven Farrell
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Patent number: 6119219Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.Type: GrantFiled: April 30, 1998Date of Patent: September 12, 2000Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Dean G. Bair, Mark Steven Farrell, Barry Watson Krumm, Pak-kin Mak, Jennifer Almoradie Navarro, Timothy John Slegel
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Patent number: 6108776Abstract: A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.Type: GrantFiled: April 30, 1998Date of Patent: August 22, 2000Assignee: International Business Machines CorporationInventors: Mark Anthony Check, John Stephen Liptay, Timothy John Slegel, Charles Franklin Webb, Mark Steven Farrell
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Patent number: 6105109Abstract: SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache structure.A new code array's write control elements include a control latch called "fill mode" for the BCE controls which when fill mode is active, then a disable is also active, since reads of the code array may not give accurate data when the array is not yet filled-up/fully valid. New mode follows the sequential steps which process code by:a) purge the cache array; thenb) disable the code array; thenc) turn on fill mode with a buffer control element fill mode latch; and then processd) code increments once through a range of line addresses, where the range is at least as wide as the range(s) specified in the code array's lookup mechanism.e) turn off fill mode; thenf) purge the cache array again: and theng) enable the code array (turn off the code array disable bit).h) resume normal operation to end the sequence.Type: GrantFiled: February 19, 1998Date of Patent: August 15, 2000Assignee: International Business Machines CorporationInventors: Barry Watson Krumm, Charles Franklin Webb, Timothy John Slegel, Mark Steven Farrell, Yuen Hung Chan
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Patent number: 6079013Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.Type: GrantFiled: April 30, 1998Date of Patent: June 20, 2000Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Dean G. Bair, Mark Steven Farrell, Barry Watson Krumm, Pak-kin Mak, Jennifer Almoradie Navarro, Timothy John Slegel
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Patent number: 6058470Abstract: A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string.Type: GrantFiled: April 7, 1998Date of Patent: May 2, 2000Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell
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Patent number: 6055624Abstract: A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string.Type: GrantFiled: April 7, 1998Date of Patent: April 25, 2000Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell, Timothy John Slegel
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Patent number: 6044454Abstract: IEEE compliant floating point unit mechanism allows variability in the execution of floating point operations according to the IEEE 754 standard and allowing variability of the standard to co-exist in hardware or in the combination of hardware and millicode. The FPU has a detector of special conditions which dynamically detects an event that the hardware execution of an IEEE compliant Binary Floating Point instruction will require millicode emulation. The complete set of events which millicode may emulate are predetermined early in the design process of the hardware. An exception handling unit assist millicode emulation by trapping the result of an exceptional condition without invoking the trap handler. When an exceptional condition is detected during execution, the IEEE 754 standard requires two different actions under control of a mask bit. If the mask bit is on, the result is written into an FPR and the trap handler is invoked.Type: GrantFiled: February 19, 1998Date of Patent: March 28, 2000Assignee: International Business Machines CorporationInventors: Eric Mark Schwarz, Christopher A. Krygowski, Timothy John Slegel, David Frazelle McManigal, Mark Steven Farrell
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Patent number: 5819078Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.Type: GrantFiled: June 10, 1997Date of Patent: October 6, 1998Assignee: International Business Machines CorporationInventors: Mark Steven Farrell, Barry Watson Krumm, Jennifer Serena Almoradie Navarro, Charles Franklin Webb
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Patent number: 5802359Abstract: A milli-mode system has a processor state unit (R-unit) with register space into which those system operating registers and control latches, which make up the processor architected state, are mapped. This processor state unit, which includes a processor state register array and associated controls, receives all state updates from the processor as data and register addresses.Type: GrantFiled: July 14, 1997Date of Patent: September 1, 1998Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell
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Patent number: 5790844Abstract: A special inillicode instruction "Load With Access Test" explicitly detects access exceptions for storage operands while retaining control in the current millicode routine to insure exceptions are handled correctly and with the right priority. The millicode Load With Access Test instruction operates similarly to the ESA/390 Load instruction except that access exception code is set, interrupts are blocked and the serialization is forced to purge the instruction pipeline and reset the pipeline control without redirection of the instruction stream.Type: GrantFiled: March 31, 1997Date of Patent: August 4, 1998Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell, Mark Anthony Check, John Stephen Liptay
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Patent number: 5754810Abstract: A millicode method for packing the hexadecimal digits from a plurality of bytes in each of two millicode registers (R1,R1) into one of the two millicode registers extracts the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R1 and the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R2 and stores hexadecimal digits from said extracting step in millicode register R1 with each hexadecimal digit extracted from a byte in register R1 and from a byte in register R2 stored in millicode register R1 in register R1 positions occupied by said plurality of bytes stored in register R1 prior to said extraction step.Type: GrantFiled: March 12, 1996Date of Patent: May 19, 1998Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell, Charles Lewis Cross, Nishit Hemantkumar Gokli, Wen He Li
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Patent number: 5748951Abstract: A special Program Status Word (PSW) millicode routine, tests the validity of the PSW with three simple millicode instructions. Testing for access exceptions is executed by a special millicode instruction "Load With Access Test", which explicitly detects access exceptions for storage operands while retaining control in the current millicode routine. A Translate and Test (TRT) routine uses a table of 256 bytes to translate a string of bytes. Each string is used as an index into the table, and the selected table byte is fetched. For Translate and Test, the selected bytes are tested, and the first non-zero table byte selected is returned to the program in a general register along with the address of the string byte which selected it; translate and test also sets the condition code, and does not update storage.Type: GrantFiled: March 31, 1997Date of Patent: May 5, 1998Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell, Mark Anthony Check, John Stephen Liptay
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Patent number: 5713035Abstract: In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.Type: GrantFiled: March 31, 1995Date of Patent: January 27, 1998Assignee: International Business Machines CorporationInventors: Mark Steven Farrell, Barry Watson Krumm, John Stephen Liptay, Charles Franklin Webb, Steven QiHong Ying
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Patent number: 5694587Abstract: A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.Type: GrantFiled: March 31, 1995Date of Patent: December 2, 1997Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell, Mark Anthony Check, John Stephen Liptay
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Patent number: 5694617Abstract: A milli-mode routine handles a quiesce interrupt, and causes all the processors in the system to enter a quiesced state. A single bit of a millicode control register indicates a quiesced state and drives an output of the processor to indicate the processor is in a quiesced state. The processor receives a signal indicating all processors in the system are in a quiesced state and latches this value. The output of this latch is sent to the processor instruction unit for use as a millicode branch condition.Type: GrantFiled: March 31, 1995Date of Patent: December 2, 1997Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Janet Rhea Easton, Mark Steven Farrell, Ming H. Cheung
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Patent number: 5684975Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.Type: GrantFiled: May 30, 1995Date of Patent: November 4, 1997Assignee: International Business Machines CorporationInventors: Karl Jean Duvalsaint, Mark Steven Farrell, Barry Watson Krumm, Donald William McCauley, Charles Franklin Webb
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Patent number: 5680598Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.Type: GrantFiled: March 31, 1995Date of Patent: October 21, 1997Assignee: International Business Machines CorporationInventors: Mark Steven Farrell, Barry Watson Krumm, Jennifer Serena Almoradie Navarro, Charles Franklin Webb
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Patent number: 5673391Abstract: Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage of the millicode sequence. The millicode routine tests the retry latch state at one or more points in the sequence to determine if a retry has occurred since the start of the sequence, which is sensitive to a retry operation. The action taken in response to a determination that a retry operation has occurred depends upon the type of potential damage to the system state as a result of the occurrence of the retry operation during the millicode sequence.Type: GrantFiled: March 31, 1995Date of Patent: September 30, 1997Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Mark Steven Farrell, Scott Barnett Swaney
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Patent number: 5649140Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.Type: GrantFiled: March 31, 1995Date of Patent: July 15, 1997Assignee: International Business Machines CorporationInventors: Karl Jean Duvalsaint, Mark Steven Farrell, Barry Watson Krumm, Donald William McCauley, Charles Franklin Webb