Abstract: The present invention relates to compounds according to general formula (I) with enhanced absorption of UV-B irradiation. The present invention also relates to an UV-B tolerant plant and a method for enhanced production of compounds according to general formula (I) in a plant or plant cell. Furthermore, the invention relates to a nucleic acid sequence SEQ-ID No. 1 encoding FPT2 catalyzing the production of compounds according to general formula (I). The invention further relates to compositions comprising compounds according to general formula (I). Furthermore, the invention relates to a method of conferring UV-B tolerance to a plant as well as an UV-B tolerant plant comprising the nucleic acid sequence SEQ-ID No. 1 encoding FPT2 catalyzing the production of compounds according to general formula (I).

Abstract: The present invention relates to compounds according to general formula (I) with enhanced absorption of UV-B irradiation. The present invention also relates to an UV-B tolerant plant and a method for enhanced production of compounds according to general formula (I) in a plant or plant cell. Furthermore, the invention relates to a nucleic acid sequence SEQ-ID No. 1 encoding FPT2 catalyzing the production of compounds according to general formula (I). The invention further relates to compositions comprising compounds according to general formula (I). Furthermore, the invention relates to a method of conferring UV-B tolerance to a plant as well as an UV-B tolerant plant comprising the nucleic acid sequence SEQ-ID No. 1 encoding FPT2 catalyzing the production of compounds according to general formula (I).

Abstract: The present invention relates to compounds according to general formula (I) with enhanced absorption of UV-B irradiation. The present invention also relates to an UV-B tolerant plant and a method for enhanced production of compounds according to general formula (I) in a plant or plant cell. Furthermore, the invention relates to a nucleic acid sequence SEQ-ID No.1 encoding FPT2 catalyzing the production of compounds according to general formula (I). The invention further relates to compositions comprising compounds according to general formula (I). Furthermore, the invention relates to a method of conferring UV-B tolerance to a plant as well as an UV-B tolerant plant comprising the nucleic acid sequence SEQ-ID No.1 encoding FPT2 catalyzing the production of compounds according to general formula (I).

Abstract: A system and a method for producing a quantified defined portions of powder from at least one biological material at cryotemperature is shown, comprising means for grinding the biological material deposited in at least one first vessel to the powder; means for loosening the powder resulting from grinding the biological material in the first vessel; means for positioning at least one first opening in the first vessel, and means for transferring the quantified defined portions of powder in a plurality of second vessels by using the first opening as a transfer way.

Abstract: A process for identifying whether plant is resistant to chilling comprises cultivating the plant at a reduced temperature for a time period selected from short term and medium term; harvesting a tissue sample of the plant; measuring concentration of at least one metabolite in the tissue sample of the plant; comparing the measured concentration with the concentration of the same metabolite in a tissue sample harvested from a reference plant or a plant of the same species after cultivation at a reference temperature; and optionally, repeating the process of foregoing steps but cultivating the plant at a reduced temperature for a time period selected from short term and medium term and not previously used; wherein resistance to chilling is indicated by one or more of the effects on metabolites listed in Table 2 or Table 4.

Abstract: A system and a method for producing a quantified defined portions of powder from at least one biological material at cryotemperature is shown, comprising means for grinding the biological material deposited in at least one first vessel to the powder; means for loosening the powder resulting from grinding the biological material in the first vessel; means for positioning at least one first opening in the first vessel, and means for transferring the quantified defined portions of powder in a plurality of second vessels by using the first opening as a transfer way.

Abstract: The invention relates to methods of increasing the total oil content and/or the glycerol 3-phosphate content in transgenic oil crop plants which comprise at least 20% by weight of oleic acid based on the total fatty acid content, preferably in plant seeds, by expressing glycerol 3-phosphate dehydrogenases (G3PDHs) from yeasts, preferably from Saccharomyces cerevisiae. The oil and/or the free fatty acids obtained in the process are advantageously added to polymers, foodstuffs, feedstuffs, cosmetics, pharmaceuticals or products with industrial applications.

Abstract: A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high voltage difference amplifier is disclosed having a calibration circuit which couples a calibration excitation signal to a common-mode signal path of the difference amplifier. The difference amplifier includes a variable transfer function circuit which may be used to adjust the common-mode rejection of the difference amplifier. The calibration excitation signal may be a random, pseudo-random, out-of-band, or other frequency shaped signal generated in reference to a clock signal. A calibration error signal is detected from an output signal. The variable transfer function circuit can be adjusted in response to the detected error signal to reduce the calibration error signal. As a result, common-mode rejection errors of the difference amplifier may be reduced while the difference amplifier is coupled to an input signal source.

Abstract: A temperature-compensated monolithic logarithmic amplifier includes a logarithmic amplifier cell (26) configured to produce a logarithmic voltage signal (V3) representative of a difference between a first voltage (V1) developed across a first PN junction device (D1) in response to an input signal (Iin) and a second voltage (V2) developed across a second PN junction device (D2) in response to a reference signal (Iref) and an output circuit (36) including an output amplifier (19), a temperature-dependent first resistive element (R1) having a positive temperature coefficient, and a second resistive element (R2). The output circuit (36) produces a temperature-compensated output signal (Vout) in response to the logarithmic voltage signal (V3). The first resistive element (R1) is composed of conductive aluminum or aluminum alloy interconnection metallization that also is utilized as interconnection metallization throughout the monolithic logarithmic amplifier.

Abstract: A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high voltage difference amplifier is disclosed having a calibration circuit which couples a calibration excitation signal to a common-mode signal path of the difference amplifier. The difference amplifier includes a variable transfer function circuit which may be used to adjust the common-mode rejection of the difference amplifier. The calibration excitation signal may be a random, pseudo-random, out-of-band, or other frequency shaped signal generated in reference to a clock signal. A calibration error signal is detected from an output signal. The variable transfer function circuit can be adjusted in response to the detected error signal to reduce the calibration error signal. As a result, common-mode rejection errors of the difference amplifier may be reduced while the difference amplifier is coupled to an input signal source.

Abstract: A leadframe is provided which has an integrated resistive element incorporated within the leadframe. The resistive element suitably comprises a material that can provide a temperature coefficient of under 500 ppm/° C., preferably approximating 100 ppm/° C. or less. Exemplary embodiments of the resistive material may include Constantan or Manganin. The leadframe and integrated resistive element may be utilized in a variety of integrated circuit applications, such as a current monitoring circuit. Accordingly, variations in temperature will not dramatically affect the accuracy of any integrated circuit devices during operation. Additionally, after encapsulation of the leadframe and integrated resistive element and any such integrated circuit device, the gain of the encapsulated circuit may be suitably adjusted by various calibration techniques.

Abstract: A low drop out voltage regulator includes an error amplifier (12) having a first input coupled to a first reference voltage (VREF), a second input receiving a feedback signal, and an output (15) producing an output signal (VAMPOUT). An output transistor (18) has a gate, a drain coupled to an unregulated input voltage (VIN), and a source coupled to produce a regulated output voltage (VOUT) on an output conductor (19). A feedback circuit (20,22) is coupled between the output conductor (19) and a reference voltage (GND) to produce the feedback signal. A capacitor (16) is coupled between the output (15) of the error amplifier and the gate (17) of the output transistor (18). A servo amplifier (24) has a first input coupled to a second reference voltage (VVREF), a second input coupled to the output (15) of the error amplifier. A low current charge pump circuit (26B) supplies an output current into a supply voltage terminal of the servo amplifier.

Abstract: An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors.

Abstract: A circuit and method for reducing an input bias current flowing from an external signal source coupled to an input terminal of the circuit, the circuit being coupled to an input device having a device leakage current related to a device voltage. According to a preferred embodiment, a replica voltage source provides a replica voltage equal to the device voltage. A cancellation device is coupled to the replica voltage source so that the replica voltage is applied to the cancellation device. The cancellation device is further coupled to the input terminal for providing a cancellation current equal to the device leakage current, wherein the input bias current is equal to the difference between the device leakage current and the cancellation current.

Abstract: A planar transformer assembly includes an insulative layer, a first spiral winding thereon circumscribing a magnetic flux path, a second spiral winding thereon in non-overlapping relation to the first spiral winding circumscribing the magnetic flux path, and a ferrite core assembly including first and second core sections defining a shallow gap or passage within which the spiral windings are disposed. In one embodiment, a plurality of laminated insulative layers are provided with a primary winding including a plurality of series-connected spiral subwindings and a non-overlapping secondary winding formed on the various insulative layers. The non-overlapping structure and the order of the various windings minimize electric field gradients and thereby minimize electric field coupled noise currents.

Abstract: An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors.

Abstract: A planar transformer includes a multilayer printed circuit board having a plurality of spiral windings formed by metalization on various surfaces of the printed circuit board. A ferrite core assembly includes first and second core sections disposed on opposite sides of the printed circuit board and completely confining the conductors of the spiral windings. Each core section includes a thin, flat plate. The two flat plates are integral with or abut thin post sections that are thick enough to allow the printed circuit board to be accommodated between the first and second core sections. In one embodiment of the invention, the planar transformer is incorporated on the printed circuit board with other circuitry to form a low noise battery charger which is encapsulated in a male power connector.

Abstract: A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.

Abstract: Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor.

Abstract: A common-base, source-driven differential amplifier achieves both high speed operation and low noise operation by providing an input stage including a pair of source follower JFETs that drive emitters of a pair of NPN input transistors having their bases connected together and to a bias circuit. The collectors of the NPN transistors each are connected to a corresponding load device and to a corresponding input of an output amplifier stage. The bias circuit includes a current source and a pair of diode-connected NPN transistors having their bases and collectors connected to the current source and to the bases of the input transistors. The emitters of the diode-connected NPN transistors are connected to sources of a second pair of source follower JFETs, the gates of which are connected to the input terminals.