Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information.

Abstract: A peripheral power control sequencer incorporates a microcomputer to control the sequencing of the powering of a plurality of peripheral control units. The terminals of the input/output ports of the microcomputer are time-shared to accommodate the several input and output signals needed to accomplish the sequential powering of the peripheral controller.