Abstract: A method of preparing an antibody therapeutic is provided comprising: (a) providing a dissociated cell sample from at least one solid tumor sample obtained from a patient; (b) loading the dissociated cell sample into a microfluidic device having a flow region and at least one isolation region fluidically connected to the flow region; (c) moving at least one B cell from the dissociated cell sample into at least one isolation region in the microfluidic device, thereby obtaining at least one isolated B cell; and (d) using the microfluidic device to identify at least one B cell that produces antibodies capable of binding to cancer cells. The cancer cells can be the patient's own cancer cells. Also provided are methods of treating patients, methods of labeling or detecting cancer, engineered T or NK cells comprising antibodies or fragments thereof, and engineered antibody constructs.

Abstract: A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in response, to send a probe to determine whether any of the other caches contain a copy of the requested data. Some time after sending the probe, the cache controller may provide a speculative response to the cache fill request to the requesting device. By delaying providing the speculative response until some time after the probes are sent, it may become more likely that the responses to the probes will be received in time to validate the speculative response.

Abstract: According to the present invention, a method for inserting scan hardware into Integrated Circuits (IC) such as microcontrollers is disclosed. Custom scripts used by electronic design automation (EDA) tools are configured to accommodate those microcontroller designs that operate with multiple clocks and legacy cores. Furthermore, according to the present invention, custom script are used to provide buffering circuits to drive the scan hardware.

Abstract: A method and apparatus for identifying framing bits embedded in an ATM frame significantly improves performance by logically comparing multiple bit slices in parallel to identify framing bits. Bits are received from a sequential input stream (64) to form an ordered collection of bits, included (66) in a frame bit history. The remainder of the bits separating framing bits are ignored (68). A second group of bits is received (70) to form another ordered collection of bits of the same size. This ordered collection of bits is included (74) in the frame bit history. Bits in the sequential input stream are again ignored (80). A third group of bits is received (82) to form another ordered collection of bits, and is included (88) in the frame bit history. The various ordered collections of bits saved in the frame bit history are logically compared (90) to determine (92) whether any of the corresponding bit slices could possibly constitute framing bits.