Abstract: Secure access and processing of an encryption/decryption key may include generating one or more keys within a key controller block of a chip. The generated keys may be transferred from the key controller block of the chip to an on-chip bus interface block via a secure serial link. The transferred keys may be stored in registers which may be accessible by only the key controller block of the chip. In this regard, the generated keys may be written to one or more of the key registers only by the key controller block. Furthermore, a written key may be read from a key register only by the key controller block. During the transfer of a generated key, a data valid signal may be used to indicate valid keys in a data signal used to transfer the keys via the secure serial link.

Abstract: Certain embodiments of the invention provide a method and system for memory to bus interface data encryption and decryption. A method for memory to bus interface data encryption and decryption may include encrypting data by a encryption/decryption engine or processor and transferring the encrypted data across a first bus interface to a data processing and/or storage device coupled to the first bus interface. The encryption engine may receive encrypted data from a device coupled to the first bus interface and decrypt the received encrypted data. In this regard, unencrypted data never traverses across the first bus interface, and is thereby not accessible to devices coupled to the first bus interface. An encryption function and a decryption function associated with the encryption/decryption engine may be integrated within a bus adapter, for example, an IDE bus adapter.

Abstract: System and method for generating and distributing an encryption/decryption key are disclosed and may include generating one or more keys by a key generator integrated within a chip. The generated one or more keys may be communicated directly from the key generator, via an on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices. A particular one of the plurality of on-chip addressable encryption/decryption devices processes one or more received packets that include its own address utilizing the one or more keys. The at least one key may be serialized and encapsulated into a key packet. The encapsulating may include encapsulating an address of the one of the plurality of on-chip addressable encryption/decryption devices in the key packet.

Abstract: Controlling an encryption/decryption device using descriptors may include formatting a first block of memory to contain a generic data template used to control the encryption/decryption device. The first memory block may be configured with actual data values corresponding to the generic data template. At least a portion of the configured actual data values may be acquired and used for controlling one or more operations of the encryption/decryption device. A second memory block may be configured in a manner compatible with the first memory block format. The second memory block may also be configured with actual data values corresponding to the generic data template of first block of memory. The second block of memory may be linked to the first memory block. The first and second block of memory may be a random access memory.

Abstract: Aspects of a method and system for a multi-standard TV audio encoder are provided. In this regard, an integrated multistandard television audio encoder may be configured to encode television audio signals using a specified television audio standard. Moreover, once configured, the multistandard television audio encoder may encode television audio signals using the specified television audio standard. Exemplary television audio standards may comprise BTSC, A2, EIA-J, and NICAM. The multistandard television audio encoder may be enabled to generate all or portions of audio signals in accordance with one or more television audio standards. The multistandard television audio encoder may be enabled to generate baseband and/or RF modulated television audio signals. Accordingly, the multistandard television audio encoder may be enabled to generate an audio portion of a composite television signal.

Abstract: System and method for generating and distributing an encryption/decryption key are disclosed and may include generating one or more keys by a key generator integrated within a chip. The generated one or more keys may be communicated directly from the key generator, via an on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices. A particular one of the plurality of on-chip addressable encryption/decryption devices processes one or more received packets that include its own address utilizing the one or more keys. The at least one key may be serialized and encapsulated into a key packet. The encapsulating may include encapsulating an address of the one of the plurality of on-chip addressable encryption/decryption devices in the key packet.

Abstract: Aspects of an encryption/decryption key generation and distribution may include generating one or more keys for use by one of a plurality of encryption/decryption devices coupled to a serial link within a chip. The generated keys may be transmitted via, for example, a high speed serial link to which one or more of the encryption/decryption devices in the chip may be coupled. The encryption/decryption devices coupled to the serial link may be adapted to examine or identify the transmitted key packets on the serial link and determine whether a particular key packet contains a key that which should be utilized by a particular one of the encryption/decryption devices. Upon identification of a key, the key may subsequently be processed and/or utilized by an integrated encryption/decryption processor associated with the encryption/decryption device to which the encryption key belongs.

Abstract: Aspects of an encryption/decryption key generation and distribution may include generating one or more keys for use by one of a plurality of encryption/decryption devices coupled to a serial link within a chip. The generated keys may be transmitted via, for example, a high speed serial link to which one or more of the encryption/decryption devices in the chip may be coupled. The encryption/decryption devices coupled to the serial link may be adapted to examine or identify the transmitted key packets on the serial link and determine whether a particular key packet contains a key that which should be utilized by a particular one of the encryption/decryption devices. Upon identification of a key, the key may subsequently be processed and/or utilized by an integrated encryption/decryption processor associated with the encryption/decryption device to which the encryption key belongs.

Abstract: Secure access and processing of an encryption/decryption key may include generating one or more keys within a key controller block of a chip. The generated keys may be transferred from the key controller block of the chip to an on-chip bus interface block via a secure serial link. The transferred keys may be stored in registers which may be accessible by only the key controller block of the chip. In this regard, the generated keys may be written to one or more of the key registers only by the key controller block. Furthermore, a written key may be read from a key register only by the key controller block. During the transfer of a generated key, a data valid signal may be used to indicate valid keys in a data signal used to transfer the keys via the secure serial link.

Abstract: Certain embodiments of the invention provide a method and system for memory to bus interface data encryption and decryption. A method for memory to bus interface data encryption and decryption may include encrypting data by a encryption/decryption engine or processor and transferring the encrypted data across a first bus interface to a data processing and/or storage device coupled to the first bus interface. The encryption engine may receive encrypted data from a device coupled to the first bus interface and decrypt the received encrypted data. In this regard, unencrypted data never traverses across the first bus interface, and is thereby not accessible to devices coupled to the first bus interface. An encryption function and a decryption function associated with the encryption/decryption engine may be integrated within a bus adapter, for example, an IDE bus adapter.

Abstract: Controlling an encryption/decryption device using descriptors may include formatting a first block of memory to contain a generic data template used to control the encryption/decryption device. The first memory bock may be configured with actual data values corresponding to the generic data template. At least a portion of the configured actual data values may be acquired and used for controlling one or more operations of the encryption/decryption device. A second memory block may be configured in a manner compatible with the first memory block format. The second memory block may also be configured with actual data values corresponding to the generic data template of first block of memory. The second block of memory may be linked to the first memory block. The first and second block of memory may be a random access memory.

Abstract: An apparatus for correcting for nonlinearities in modulation systems includes a transmitter (24, 28, 48, 50, 52) for transmitting a time varying modulated radar signal (56). A receiver (58, 62) receives an echo signal (60) resulting from reflection of the transmitted modulated signal (56). A mixer (48) compares the transmitted signal against the echo signal and providing a comparison signal indicative of the comparison. The comparison signal is sampled by an A/D converter (74). The A/D convertor (74) provides a sampled comparison signal to a controller/DSP (22). Controller/DSP (22) resamples the sampled comparison signal at selected resample times and effectively varies the selected resample times to correct for nonlinearities in the comparison signal resulting from nonlinearities of the transmitted time varying modulated signal.