Abstract: A method for validating that an integrated circuit die is not susceptible to a conductive metallic ion diffusion defect is disclosed. A test component is applied to a backside surface of the integrated circuit die to form a test assembly. The test component includes a conductive metal layer and a transport media layer for facilitating diffusion of conductive metallic ions. The test assembly is heated at a thermal activation temperature. The integrated circuit die is computer validated to determine whether or not the integrated circuit die has the conductive metallic ion diffusion defect.

Abstract: A method for validating that an integrated circuit die is not susceptible to a conductive metallic ion diffusion defect is disclosed. A test component is applied to a backside surface of the integrated circuit die to form a test assembly. The test component includes a conductive metal layer and a transport media layer for facilitating diffusion of conductive metallic ions. The test assembly is heated at a thermal activation temperature. The integrated circuit die is computer validated to determine whether or not the integrated circuit die has the conductive metallic ion diffusion defect.

Abstract: Techniques for graphic formation via material ablation described. In at least some implementations, a graphic is applied to a surface of an object by ablating layers of the object to form an ablation trench in the shape of the graphic. In at least some embodiments, an object can include a surface layer and multiple sublayers of materials. When an ablation trench is generated in the object, the ablation trench can penetrate a surface layer of the object and into an intermediate layer. In at least some implementations, height variations in an object surface caused by an ablation trench can cause variations in light reflection properties such that a graphic applied via the ablation trench appears at a different color tone than a surrounding surface, even if the ablation trench and the surrounding surface are coated with a same colored coating.

Abstract: An electronic device includes an electronic component configured to receive electric current and a plated contact electrically coupled to the electronic component and configured to carry the electric current to the electronic component from a system external to the device. The plated contact includes a copper-alloy layer, a platinum-group metal (PGM) layer plated over the copper-alloy layer, and a gold-alloy layer plated over the PGM layer.

Abstract: Techniques for graphic formation via material ablation described. In at least some implementations, a graphic is applied to a surface of an object by ablating layers of the object to form an ablation trench in the shape of the graphic. In at least some embodiments, an object can include a surface layer and multiple sublayers of materials. When an ablation trench is generated in the object, the ablation trench can penetrate a surface layer of the object and into an intermediate layer. In at least some implementations, height variations in an object surface caused by an ablation trench can cause variations in light reflection properties such that a graphic applied via the ablation trench appears at a different color tone than a surrounding surface, even if the ablation trench and the surrounding surface are coated with a same colored coating.

Abstract: An electronic device includes an electronic component configured to receive electric current and a plated contact electrically coupled to the electronic component and configured to carry the electric current to the electronic component from a system external to the device. The plated contact includes a copper-alloy layer, a platinum-group metal (PGM) layer plated over the copper-alloy layer, and a gold-alloy layer plated over the PGM layer.

Abstract: Techniques for graphic formation via material ablation described. In at least some implementations, a graphic is applied to a surface of an object by ablating layers of the object to form an ablation trench in the shape of the graphic. In at least some embodiments, an object can include a surface layer and multiple sublayers of materials. When an ablation trench is generated in the object, the ablation trench can penetrate a surface layer of the object and into an intermediate layer. In at least some implementations, height variations in an object surface caused by an ablation trench can cause variations in light reflection properties such that a graphic applied via the ablation trench appears at a different color tone than a surrounding surface, even if the ablation trench and the surrounding surface are coated with a same colored coating.

Abstract: A method for producing a circuit board having an integrated electronic component comprising providing a circuit board substrate having a first substrate surface and a second substrate surface, securing an integrated electronic component to the first substrate surface, and disposing a first dielectric layer on the first substrate surface and over the first integrated electronic component. The method additionally includes disposing a metallic layer on the first dielectric layer to produce an integrated electronic component assembly, producing in the integrated electronic component assembly at least one via having a metal lining in contact with the metallic layer, and disposing a second dielectric layer over the via and over the metallic layer.

Abstract: A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium.

Abstract: A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

Abstract: A method for joining large area semiconductor substrates, a liquid thermoset polymer. Two large area substrates, such as wafers or circuit boards (e.g., rigid or flexible), can be joined together by dispensing a liquid polymer inwardly from the edges of the semiconductor substrates. The substrates can then be pressed together so that the liquid thermoset flows in an outwardly direction ward the edges of the semiconductor substrates. Conducting surfaces on the first and second substrates may contact each other after pressing the liquid thermoset polymer. The liquid thermoset polymer in the formed structure may then be cured to a hardened state. The liquid thermoset polymer preferable has a low viscosity, low levels of ionic contaminants, good adhesion to the substrates, low moisture absorbing properties and favorable thermal expansion properties.

Abstract: A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium.

Abstract: A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium.

Abstract: An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide.

Abstract: A method for transferring devices to a device substrate is disclosed. In one embodiment, the method includes providing an array of devices on a carrier substrate having a generally horizontal surface, where the array comprises multiple device pluralities. The method includes tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate. Each tilted device plurality is preferably in substantially the same pattern, and each tilted device plurality is placed on device regions on respective device substrates.

Abstract: A conductive composition, and articles and methods using the conductive composition are disclosed.

Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure.

Abstract: A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium.

Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure. Plasma may be used to treat a surface of the release layer or the dielectric film to produce a plasma-treated surface to lower the peel strength of any film or layer bound to the plasma-treated surface.

Abstract: A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A method for fabricating a composite interposer comprising disposing a silicon layer on a substrate, and selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate. Vias are formed through the exposed part of the substrate. The method additionally includes filling the vias and the silicon openings with a filler material (e.g.