Abstract: A method and apparatus for compression/decompression and filtering of a signal in which the apparatus has an input register (704) which receives the received signal, an output register (712) which transmits a processed signal and a distributed arithmetic processor (708) having a plurality of operational modes. The distributed arithmetic processor is coupled to the input register by an input path and is coupled to the output register by an output path. The apparatus also has a DCT butterfly processor (706) selectively switched into the input path in response to selection of a predetermined operational mode from the plurality of operational modes. An IDCT butterfly processor (710) is also selectively switched into the output path in response to the selection of one of the predetermined operational modes. Additionally, the apparatus selectively functions as a FIR filter with both the DCT butterfly processor (706) and IDCT butterfly processor (710) removed from the input and output paths.

Abstract: A method and apparatus for compression/decompression and filtering of a signal in which the apparatus has an input register (704) which receives the received signal, an output register (712) which transmits a processed signal and a distributed arithmetic processor (708) having a plurality of operational modes. The distributed arithmetic processor is coupled to the input register by an input path and is coupled to the output register by an output path. The apparatus also has a DCT butterfly processor (706) selectively switched into the input path in response to selection of a predetermined operational mode from the plurality of operational modes. An IDCT butterfly processor (710) is also selectively switched into the output path in response to the selection of one of the predetermined operational modes. Additionally, the apparatus selectively functions as a FIR filter with both the DCT butterfly processor (706) and IDCT butterfly processor (710) removed from the input and output paths.

Abstract: The present invention provides an auxiliary catalytic converter having a back pressure relief device being disposed after the main catalytic converter or after the muffler system which further reduces vehicle exhaust emissions from exhaust emission systems and that will meet the more stringent emission requirements of state and federal government regulations. The auxiliary catalytic converter includes a ceramic or steel housing of relatively small size, having a diameter in the range of 1 inch to 8 inches and a length of 4 inches to 11 inches. The housing includes a matrix core of catalytic layered materials which react with the gaseous exhaust emission pollutants, such as NO.sub.x, NHMC, HC, and CO. These pollutants are further reduced and oxidized by the auxiliary catalytic converter using typical catalytic materials of platinum, palladium, rhodium, or the like contained within the honeycombed or meshed layers of the matrix core.

Abstract: A catalytic converter for a tailpipe which further reduces vehicle exhaust emissions from exhaust emission systems and that will meet the more stringent emission requirements of state and federal government regulations. The tailpipe catalytic converter includes a ceramic or steel housing which includes a matrix core of catalytic layered materials which react with the exhaust emission pollutants, such as NO.sub.x, NMHC, HC, and CO. These pollutants are further reduced and oxidized by the catalytic converter in the tailpipe by the typical catalytic materials of platinum, palladium, rhodium, or the like contained within the honeycombed or meshed layers of the matrix core. The catalytic converter is lodged within the interior of the tailpipe adjacent the open end or as an extension to the end of the tailpipe. The tailpipe catalytic converter is held in place by any suitable device, such as a clamp, mounting screws, or mounting brackets.

Abstract: A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access.sub.-- size value. The access.sub.-- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of "1" bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.