Abstract: Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

Abstract: Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

Abstract: Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

Abstract: Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

Abstract: Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

Abstract: Systems and methods for decoding compressed data are described herein. A memory may receive a data stream comprising a string of encoded symbols encoded using an arithmetic coding based coding technique. The string of encoded symbols represents a series of one or more decoded symbols. Each of the one or more decoded symbols comprises one of a most probable symbol and a least probable symbol. A processor may determine a number of consecutive most probable symbols in the series of one or more decoded symbols by performing a plurality of parallel mathematical comparisons based on one or more of the encoded symbols. The processor may further decode a group of symbols of the series of one or more decoded symbols based on the plurality of parallel mathematical comparisons. The group of symbols comprises the number of consecutive most probable symbols.

Abstract: Systems and methods for decoding compressed data are described herein. A memory may receive a data stream comprising a string of encoded symbols encoded using an arithmetic coding based coding technique. The string of encoded symbols represents a series of one or more decoded symbols. Each of the one or more decoded symbols comprises one of a most probable symbol and a least probable symbol. A processor may determine a number of consecutive most probable symbols in the series of one or more decoded symbols by performing a plurality of parallel mathematical comparisons based on one or more of the encoded symbols. The processor may further decode a group of symbols of the series of one or more decoded symbols based on the plurality of parallel mathematical comparisons. The group of symbols comprises the number of consecutive most probable symbols.

Abstract: Electromechanical devices such as MEMS can be controlled by “drive schemes” comprising electrical signals applied to the display to cause selective actuation or release of the electromechanical devices. In some drive schemes, all pixels on a line are released during a phase when a release voltage is applied along the common line. In some invention embodiments, the release phase sets the common line voltage to the maximum segment drive voltage for a portion of the release phase and the minimum segment drive voltage for the remainder of the release phase. This ensures that all electromechanical devices have a resulting voltage of zero during a portion of the release phase sufficient to release the devices without regard to the segment line voltages. This scheme eliminates slow and no release problems and also eliminates the need for additional voltage transitions on the segment lines.

Abstract: An electronic handheld tutorial device having a display, an input element, a memory and a processor. The memory contains databases to enable a user to prepare for a test. The processor processes inputs from a user received from the input element and administers the test and provides a complete diagnostic analysis for the results of the test on the display.

Abstract: A number of memory locations are reserved in computer memory to store pointers which indicate an address within streams of sequentially arranged data. The data stream to be scanned is selected. To scan the information stored within the data stream, a single register is provided to increment the pointer corresponding to that data stream. The pointer information is then incremented and stored into the reserved memory location. The process of selecting, scanning, incrementing, and storing may repeat for each data stream to which access is sought.

Abstract: A hand held electronic data processing device has an input keyboard and a display screen. A sixteen bit central processing unit (CPU) address bus addresses read only memory (ROM) and random access memory (RAM). However, a twenty bit register provides a twenty line address bus that is employed for addressing sequential data in ROM. A direct memory access (DMA) unit provides direct transfer of data from RAM to a forty bit register which controls the state of the pixels in a 240 character liquid crystal display (LCD). The keyboard is connected in an electronic matrix with rows driven by signals applied by system address bus lines. These various functions require exclusive use of the system address bus.