Abstract: Described embodiments provide for, in a receiver circuit, an adaptation process that adjusts the IQ-skew automatically to obtain proper eye centering in a data eye, thereby maximizing horizontal margin of the eye. The IQ-skew adaptation algorithm is realized with a ‘biased’ bang-bang phase detector (BBPD) oof a clock and data recovery circuit (CDR) that biases the weights applied to UP and DOWN outputs of the phase detector, rather than treating them equally. By weighting the BBPD UPs and DOWNs differently, the system locks to the left and right inner corners, and thereby is able to locate the center of the inner eye.

Abstract: Methods and apparatus are provided for automatic gain control in a receiver using samples taken at a desired sampling phase and target voltage level. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal substantially at a desired sampling phase (such as a center of a given unit interval), wherein at least one of the samples is taken substantially at a target voltage level; comparing the plurality of samples to determine whether the received signal has an amplitude that is substantially equal to the target voltage level; and adjusting a receiver gain based on whether the received signal amplitude is substantially equal to the target voltage level. The comparison can comprise the evaluation of a logic function, such as an exclusive OR function. The comparison can be performed over a plurality of samples to obtain an average gain update decision.

Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Abstract: In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.

Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Abstract: In described embodiments, adaptive equalization of a signal in, for example, Serializer/De-serializer transceivers by a) monitoring a data eye in a data path with an eye detector for signal amplitude and/or transition; b) setting the equalizer response of at least one equalizer in the signal path while the signal is present for statistical calibration of the data eye; c) monitoring the data eye and setting the equalizer during periods in which received data is allowed to contain errors (such as link initiation and training periods) and periods in which receive data integrity is to be maintained (such as normal data communication).

Abstract: Methods and apparatus are provided for automatic gain control in a receiver using samples taken at a desired sampling phase and target voltage level. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal substantially at a desired sampling phase (such as a center of a given unit interval), wherein at least one of the samples is taken substantially at a target voltage level; comparing the plurality of samples to determine whether the received signal has an amplitude that is substantially equal to the target voltage level; and adjusting a receiver gain based on whether the received signal amplitude is substantially equal to the target voltage level. The comparison can comprise the evaluation of a logic function, such as an exclusive OR function. The comparison can be performed over a plurality of samples to obtain an average gain update decision.

Abstract: In one embodiment, a Universal Serial Bus (USB) system assigns a first priority level to a first USB endpoint and a second priority level that is lower than the first priority level to a second USB endpoint. The USB system has memory that stores first USB data packets corresponding to the first priority level and second USB data packets corresponding to the second priority level. The USB system also has a controller that manages transfers of (i) the first USB data packets to the first USB endpoint and (ii) the second USB data packets to the second USB endpoint. If the memory concurrently stores first and second USB data packets, then the controller determines an order for transferring the first and second USB data packets based on the second priority level being lower than the first priority level and/or detection of a starvation condition for the second endpoint.

Abstract: In described embodiments, adaptive equalization of a signal in, for example, Serializer/De-serializer transceivers by a) monitoring a data eye in a data path with an eye detector for signal amplitude and/or transition; b) setting the equalizer response of at least one equalizer in the signal path while the signal is present for statistical calibration of the data eye; c) monitoring the data eye and setting the equalizer during periods in which received data is allowed to contain errors (such as link initiation and training periods) and periods in which receive data integrity is to be maintained (such as normal data communication).

Abstract: In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.

Abstract: Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of “early” and “late” corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

Abstract: Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.

Abstract: In one embodiment, a Universal Serial Bus (USB) system assigns a first priority level to a first USB endpoint and a second priority level that is lower than the first priority level to a second USB endpoint. The USB system has memory that stores first USB data packets corresponding to the first priority level and second USB data packets corresponding to the second priority level. The USB system also has a controller that manages transfers of (i) the first USB data packets to the first USB endpoint and (ii) the second USB data packets to the second USB endpoint. If the memory concurrently stores first and second USB data packets, then the controller determines an order for transferring the first and second USB data packets based on the second priority level being lower than the first priority level and/or detection of a starvation condition for the second endpoint.

Abstract: It is described a method to measure a fill level of a material by transmitting an ultrasonic or microwave signal towards a surface of the material using a level gauge arranged above the material surface, receiving in said level gauge an ultrasonic or microwave signal portion reflected from said material surface, measuring a temperature at least one measurement point between the level gauge and the material surface and determining in a calculation unit of the level gauge a temperature-corrected value of the fill level based on the time delay of the received signal portion with respect to the emitted signal and the measured temperature. To provide an improved level measuring method and system with increased reactivity and accuracy in compensating temperature variations at least one non-contact infrared thermometer is used to measure the temperature.

Abstract: Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of “early” and “late” corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

Abstract: Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.

Abstract: A barrier net (12) across a space defined by the fuselage (6) of an aircraft and a floor (7) of the aircraft comprising a first plurality of parallel lengths (13) orientated in a first direction transverse to a second plurality of parallel lengths (14) orientated in a second direction wherein the lengths (13, 14) have fastening means at each end which provide a means for fastening the net to attachment points on the aircraft fuselage (6), characterised in that neither the first nor the second plurality of lengths (13, 14) is parallel to said floor (7).

Abstract: A method and apparatus for damping an ultrasonic transducer suitable for time of flight ranging and level measurement systems. The ultrasonic transducer comprises a damping component which absorbs vibrations in the transducer to reduce the ringing effect. The damping component is subjected to plasma etching to produce a surface which readily bonds to component(s) of the transducer. According to one aspect, the damping component is formed from an inert elastomer, such as silicone rubber, and the transducer component is made of stainless steel.

Abstract: A barrier net across a space defined by the fuselage of an aircraft and a floor of the aircraft comprises a plurality of intersecting net members, at least some of the members being attached to the fuselage by attachment structures attached to attachment points on the fuselage of the aircraft and held forward of the attachment points so that a major portion of the net is in a plane further forward than the attachment points.

Abstract: Quality of Service (QoS) mechanisms and facilities are introduced into USB-based wireless Local Area Networking (LAN) communication systems. Techniques are provided for managing multiple priority queues in USB-based wireless communications systems, and for ensuring that lower priority traffic is not precluded from accessing the medium during sustained periods of use by high(er) priority traffic. A method is provided to resolve Quality of Service issues in emerging high-speed USB-based communications systems by offering support for multiple queue management within the system. A further embodiment provides an escalation mechanism for the purposes of mitigating low priority class data starvation in these communications systems, when it becomes an issue.