Abstract: The present disclosure relates to a method wherein a random value, generated by a random number generator, is stored, by a finite state machine coupled to the generator by a first dedicated bus, in a memory area of a non-volatile fuse-type memory of an integrated circuit, the memory area being only accessible by the finite state machine.

Abstract: The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.

Abstract: A monitor includes a register configured to store at least two contexts and a context change value. A context selector is configured to select at least one of the two contexts for context monitoring. The selection is made dependent on whether the context change value matches a first part of a memory access address.

Abstract: An apparatus may include a delay line having a first delay value corresponding to first operating conditions of the apparatus and a second delay value corresponding to second operating conditions of the apparatus. A monitoring circuit may monitor a time taken for a first clock edge of a clock signal to propagate through the delay line. A determining circuit may determine whether operating conditions of the apparatus are acceptable in response to the time taken.

Abstract: Corruption in a key stored in a memory is detected by reading a key from a key memory and determining if detection bits of the key read from the key memory correspond to an expected value. The expected value is a value of the detection bits of the key when the key is written to the key memory.

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract: This invention relates to a method of receiving a first potentially unreliable clock signal having a first frequency; receiving a second reliable clock signal having a second frequency; wherein the first frequency and the second frequency have an expected relationship; determining whether the first potentially unreliable clock signal has changed with respect to the second reliable clock signal by: determining an actual relationship between the first potentially unreliable frequency and the second reliable frequency; and generating an alarm signal if the actual relationship is different to the expected relationship.

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract: An apparatus may include a delay line having a first delay value corresponding to first operating conditions of the apparatus and a second delay value corresponding to second operating conditions of the apparatus. A monitoring circuit may monitor a time taken for a first clock edge of a clock signal to propagate through the delay line. A determining circuit may determine whether operating conditions of the apparatus are acceptable in response to the time taken.

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract: Corruption in a key stored in a memory is detected by reading a key from a key memory and determining if detection bits of the key read from the key memory correspond to an expected value. The expected value is a value of the detection bits of the key when the key is written to the key memory.

Abstract: This invention relates to a method of receiving a first potentially unreliable clock signal having a first frequency; receiving a second reliable clock signal having a second frequency; wherein the first frequency and the second frequency have an expected relationship; determining whether the first potentially unreliable clock signal has changed with respect to the second reliable clock signal by: determining an actual relationship between the first potentially unreliable frequency and the second reliable frequency; and generating an alarm signal if the actual relationship is different to the expected relationship.

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract: Methods of using modified lecithin to delivery various benefits to plants and plant parts are disclosed. Modified lecithins, applied to growing plants, can cause improvements in fruit and plant firmness, size, color and stability, in economically important fruits and vegetables.

Abstract: The present invention provides a storage stable microemulsion formulation for modified lecithin as well as other materials. For modified lecithin, the microemulsion contains at least one metal chelate complex, at least one surfactant such as an anionic surfactant, modified lecithin, water, and optionally at least one alcohol. For other materials, the microemulsion contains all above plus one or more other materials wherein modified lecithin can be replaced by unmodified lecithin. Further provided are methods of making and using the above microemulsions.

Abstract: The present invention relates to novel compositions comprising porous materials infused with polymers obtained from metathesis reactions, for example ROMP derived polymers and ADMET derived polymers. The invention further relates to cyclic olefin monomer formulations, including ruthenium or osmium carbene metathesis catalysts, useful for the infusion of porous materials. Also disclosed are methods for preparing the porous materials infused with cyclic olefin resin formulations.

Abstract: The invention provides novel organometallic complexes useful as olefin metathesis catalysts. The complexes have an N-heterocyclic carbene ligand and a chelating carbene ligand associated with a Group 8 transition metal center. The molecular structure of the complexes can be altered so as to provide a substantial latency period. The complexes are particularly useful in catalyzing ring closing metathesis of acyclic olefins and ring opening metathesis polymerization of cyclic olefins.

Abstract: Branched polyarylene polymers are provided comprising monovalent endcappers, divalent linear units, and polyvalent branching units. The composition of the polymers is controlled by adjusting the ratio of the three types of monomers.

Abstract: Methods of using modified lecithin to delivery various benefits to plants and plant parts are disclosed. Modified lecithins, applied to growing plants, can cause improvements in fruit and plant firmness, size, color and stability, in economically important fruits and vegetables.

Abstract: Disclosed is a device for secured access to applications of a chip card, bringing into operation instructions that provide information, at each point in time, on the rights, especially in terms of access to the chip card, of a software component or a hardware action performed in the chip card. In the case of each new software component and at each new hardware action, a register R of the microprocessor of the chip card stores a specific code that makes it possible to check the authorized nature of the operations of access to the memory of the chip card that are performed by the new software component or hardware action.