Abstract: A data processing system is disclosed that includes a data processing unit and a codec unit. A set of addresses of an address space is associated with the codec unit, and the codec unit, in response to a request from the data processing unit to access an address of the set of addresses associated with the codec unit, provides decoded data to the data processing unit or causes data provided by the data processing unit to be encoded.

Abstract: An apparatus comprises a plurality of hardware counters each corresponding to a separate sub-range of a contiguous range of target values, and histogram control circuitry to perform an indexing operation to identify and increment a selected hardware counter corresponding to a selected sub-range comprising an input value. Responsive to a histogram range update trigger, adding circuitry adds a count value of one or more first hardware counters corresponding to one or more first sub-ranges to a second hardware counter corresponding to a second sub-range neighbouring the one or more first sub-ranges, and the histogram control circuitry updates a previous indexing operation to an updated indexing operation, wherein the updated indexing operation identifies one of the one or more first hardware counters in response to an input value lying within a newly defined sub-range of the contiguous range of target values.

Abstract: An apparatus comprises invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation; cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry.

Abstract: An apparatus comprises invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation; cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry.

Abstract: A graphics processor and method of operating a graphics processor to perform rendering followed by post-processing, in which post-processing tasks are permitted to be issued to processing cores of the graphics processor without waiting for all of the rendering tasks to have completed their processing, such that post-processing tasks are processed concurrently with rendering tasks.

Abstract: When performing rendering in a graphics processor that comprises plural rendering processors each operable to render regions that a render output is divided into for allocation to the rendering processors, the processing of one or more render outputs by the rendering processors is tracked and the allocation of different regions of a render output to different ones of the rendering processor for processing is controlled based on the tracking of the processing of one or more render outputs by the rendering processors.

Abstract: When performing rendering in a graphics processor that comprises plural rendering processors each operable to render one or more regions that a render output is divided into for allocation to the rendering processors, the allocation of the regions to the rendering processors is controlled based on an amount of processing expected to be required to be performed to process different ones of the regions of the render output.

Abstract: When performing a sequence of rendering jobs, rendering tasks for separate rendering jobs are permitted to overlap within the graphics processor's processing (shader) cores. A record is maintained of which rendering tasks are currently being processed by the graphics processor's processing (shader) cores which record can then be used to enforce any data (processing) dependencies between different rendering jobs.

Abstract: The present disclosure relates to a graphics processor having a plurality of programmable execution units operable to process tasks of a first task type, a subset of the plurality of programmable execution units further operable to process tasks of a second task type, wherein the second task type is different to the first task type, and restricting a capacity of the subset of programmable execution units to process one or more tasks of a first task type when tasks of both the first task type and the second task type are to be allocated to the programmable execution units.

Abstract: A graphics processor and method of operating a graphics processor to perform rendering followed by post-processing, in which post-processing tasks are permitted to be issued to processing cores of the graphics processor without waiting for all of the rendering tasks to have completed their processing, such that post-processing tasks are processed concurrently with rendering tasks.

Abstract: Disclosed is a method of operating a graphics processor when performing a processing pass that includes an initial “pilot” processing job that executes a respective initial “pilot” shader program that is to be executed in advance of a corresponding “main” shader program that will be executed for a separate “main” processing job within the same processing pass. A “main” processing job is permitted to be issued for processing concurrently with an initial “pilot” processing job on which it depends. To enforce dependencies between “main” and “pilot” shader execution in this case it is tracked whether any initial “pilot” processing jobs are currently being processed by the set of one or more processing cores and processing of tasks for “main” processing jobs is controlled accordingly.

Abstract: Data processing systems, methods, computer program products, devices, and graphics processors are provided that substantially remove, or reduce, latencies introduced or incurred by a (host) processor e.g. a central processing unit (CPU), during virtualisation, in which virtual machines that are operable to execute on the (host) processor are scheduled or assigned to the graphics processor in a time-slice manner.

Abstract: When performing a sequence of rendering jobs, rendering tasks for separate rendering jobs are permitted to overlap within the graphics processor's processing (shader) cores. A record is maintained of which rendering tasks are currently being processed by the graphics processor's processing (shader) cores which record can then be used to enforce any data (processing) dependencies between different rendering jobs.

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks for different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks are enforced.

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced. In particular, there is disclosed a mechanism for suspending the sequence of rendering jobs (so that it may subsequently be resumed).

Abstract: A method of preparing a command stream for a parallel processor, comprising: analysing the command stream to detect at least a first dependency; generating at least one timeline dependency point responsive to detecting the first dependency; determining a latest action for the first dependency to derive a completion stream timeline point for the first dependency; comparing the completion stream timeline point for the first dependency with a completion stream timeline point for a second dependency to determine a latest stream timeline point; generating at least one command stream synchronization control instruction according to the latest stream timeline point; and providing the command stream and the at least one command stream synchronization control instruction to an execution unit of the parallel processor.

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.

Abstract: A data processing system is disclosed that includes one or more processors that can perform producer processes to produce work and consumer processes that can consume work produced by a producer process. The system includes a pool of plural communication resources that may be used for communications between a producer process and a consumer process. The system tracks the usage of communication resources of the pool of communication resources, and allocates a communication resource from the pool of communication resources based on the tracking.

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.