Abstract: An embedded-controller-based system, such as a personal digital assistant (PDA), includes a system-on-a-chip with a processor, system bus, memory, and system-bus peripherals. The system-bus peripherals include connections to data paths that are not accessible from the system bus during execution of application programs. Associated with these connections are test drivers that include registers that can be written to by the processor via the system bus for software controllability. When the processor executes a test program, it writes test values to these registers. Some bits of the test values are used to control multiplexers so that they can decouple function block ports from the non-system-bus connections and then couple the remaining bits of the registers. In this way, a test program can write data directly to the non-system bus connections. The results of the test data being applied at the source of inter-block connections can be read from the destinations using test samplers.

Abstract: A multiprocessor system comprises a series of processors arranged to process data in an assembly-line fashion. Each processor includes an executor (execution unit, instruction decoder, and program counter) and a set of registers. Each set of registers is divided into two banks. At any given time, one bank is the “active” bank that is accessible by the local processor, and the other is the “shadow” bank, inaccessible to the local processor. Each processor but the last writes in parallel to its active bank and to the shadow bank of the immediate downstream processor. When all processors have completed working the data in their respective possession, a context-switch is performed switching register banks so that former active banks become shadow banks and former shadow banks become active banks. This makes data that was being processed by an upstream processor virtually immediately available to a local processor.

Abstract: A multiplier compiler produces a schematic of a high-speed, multi-format multiplier. The compiler receives user information which indicates design preferences. Based on the user information the compiler can select the format of numbers which the multiplier will multiply and/or select a type of adder with which to implement the final adder row of the multiplier. The compiler generates user readable schematics of the multiplier. The schematic displays discrete components of the multiplier arranged in locations which show to the user the flow of logic of the circuit. Additionally, the compiler generates test vectors.