Abstract: A frequency synthesizer device with a fast off-to-lock time to enable intermittent operation and achieve power savings through automatic control of its On/Off sequence. A relatively fast off-to-lock time is achieved by controlling the sequence of how various components of the synthesizer are reactivated. The voltage controlled oscillator is reactivated, at first operating at its previous operating frequency prior to being deactivated. The phase frequency detector is inhibited while its input signals, a reference signal and a feedback signal, are activated. In a channel hopping communication scheme, the phase frequency detector coarsely tunes the synthesizer to its previous operating frequency, and then jumps to its new operating frequency. Another aspect of the invention provides improved channel locking by guaranteeing that the phase of the feedback signal in a phase lock loop initially lags the phase of the reference frequency signal at the phase frequency detector.

Abstract: A novel method and apparatus for calibrating DC offsets in a direct conversion receiver. The present DC offset calibration method and apparatus comprises a direct conversion receiver equipped with a frequency shifter means and a DC offset measurement and correction technique. In accordance with the present invention, DC offsets are calibrated in direct conversion receivers through an inventive method including two steps: a DC offset measurement step and a DC offset correction step. In the DC offset measurement step the frequency of a local oscillation signal (typically generated by a voltage-controlled oscillator (VCO)) is shifted by a selected frequency shift value during the inactive time intervals of the receiver. DC offsets are measured while the frequency of the down-conversion oscillation signal is shifted by the frequency shift value. Before the inactive time interval expires, the frequency of the down-conversion oscillator signal is shifted back to its original value.