Patents by Inventor Mark V. Raymond
Mark V. Raymond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11621333Abstract: One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.Type: GrantFiled: August 29, 2019Date of Patent: April 4, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Patent number: 10727308Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.Type: GrantFiled: August 22, 2019Date of Patent: July 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Patent number: 10643893Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.Type: GrantFiled: June 29, 2016Date of Patent: May 5, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita
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Patent number: 10580696Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.Type: GrantFiled: August 21, 2018Date of Patent: March 3, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Sean Xuan Lin, Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan
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Publication number: 20200066585Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Sean Xuan Lin, Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan
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Publication number: 20190386107Abstract: One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Publication number: 20190378900Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.Type: ApplicationFiled: August 22, 2019Publication date: December 12, 2019Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Patent number: 10490641Abstract: One illustrative method disclosed includes, among other things, forming a conductive source/drain metallization structure adjacent a gate, forming a gate contact opening that exposes at least a portion of a front face of the conductive source/drain metallization structure and a portion of an upper surface of a gate structure of the gate. In this example, the method further includes forming an internal insulating spacer within the gate contact opening that is positioned on and in contact with the exposed portion of the front face, wherein the spacer leaves at least a portion of the upper surface of the gate structure exposed, and forming a conductive gate contact structure (CB) in the conductive gate contact opening.Type: GrantFiled: April 28, 2017Date of Patent: November 26, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Patent number: 10483363Abstract: One method includes forming a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap positioned above the gate structure, forming a conductive source/drain metallization structure adjacent the gate in each of the source/drain regions and forming a recess in each of the conductive source/drain metallization structures. The method further includes forming a spacer structure that comprises recess filling portions that substantially fill the recesses and a portion that extends across the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, forming an insulating material within the spacer structure and on the exposed portion of the gate cap, forming a gate contact opening that exposes a portion of an upper surface of the gate structure and forming a conductive gate contact structure (CB) in the conductive gate contact opening.Type: GrantFiled: April 28, 2017Date of Patent: November 19, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Patent number: 10283372Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.Type: GrantFiled: September 15, 2017Date of Patent: May 7, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Sean Xuan Lin, Xunyuan Zhang, Mark V. Raymond, Errol Todd Ryan, Nicholas V. LiCausi
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Publication number: 20190088500Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Sean Xuan Lin, Xunyuan Zhang, Mark V. Raymond, Errol Todd Ryan, Nicholas V. LiCausi
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Publication number: 20190081145Abstract: A structure and method for forming sets of contact structures to source/drain regions of complimentary N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The structure including a NFET structure including a first fin positioned on a substrate and a PFET structure including a second fin positioned on the substrate, wherein a source/drain region (S/D) of the first fin and a S/D of the second fin include non-uniform openings at an uppermost surface. A method of forming non-uniformly openings in the S/Ds of the complimentary NFETs and PFETs including forming mask on the PFET to protect the structure during formation of openings in the NFET S/D. A method of forming non-uniform openings in the S/D of the complimentary NFETs and PFETs including reducing the epitaxially growth of the NFET S/D to form an opening therein.Type: ApplicationFiled: September 12, 2017Publication date: March 14, 2019Inventors: Ruilong Xie, Christopher M. Prindle, Nigel G. Cave, Mark V. Raymond
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Patent number: 10204994Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.Type: GrantFiled: April 3, 2017Date of Patent: February 12, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Chanro Park, Andre P. Labonte, Lars W. Liebmann, Nigel G. Cave, Mark V. Raymond, Guillaume Bouche, David E. Brown
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Publication number: 20190027580Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.Type: ApplicationFiled: July 20, 2017Publication date: January 24, 2019Inventors: Su Chen Fan, Andrew M. Greene, Sean Lian, Balasubramanian Pranatharthiharan, Mark V. Raymond, Ruilong Xie
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Patent number: 10186599Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.Type: GrantFiled: July 20, 2017Date of Patent: January 22, 2019Assignee: International Business Machines CorporationInventors: Su Chen Fan, Andrew M. Greene, Sean Lian, Balasubramanian Pranatharthiharan, Mark V. Raymond, Ruilong Xie
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Publication number: 20180366372Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.Type: ApplicationFiled: June 19, 2017Publication date: December 20, 2018Inventors: Puneet H. Suvarna, Steven Bentley, Mark V. Raymond, Peter M. Zeitzoff
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Patent number: 10157794Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.Type: GrantFiled: June 19, 2017Date of Patent: December 18, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Puneet H. Suvarna, Steven Bentley, Mark V. Raymond, Peter M. Zeitzoff
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Publication number: 20180315822Abstract: One method includes forming a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap positioned above the gate structure, forming a conductive source/drain metallization structure adjacent the gate in each of the source/drain regions and forming a recess in each of the conductive source/drain metallization structures. The method further includes forming a spacer structure that comprises recess filling portions that substantially fill the recesses and a portion that extends across the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, forming an insulating material within the spacer structure and on the exposed portion of the gate cap, forming a gate contact opening that exposes a portion of an upper surface of the gate structure and forming a conductive gate contact structure (CB) in the conductive gate contact opening.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Publication number: 20180315821Abstract: One illustrative method disclosed includes, among other things, forming a conductive source/drain metallization structure adjacent a gate, forming a gate contact opening that exposes at least a portion of a front face of the conductive source/drain metallization structure and a portion of an upper surface of a gate structure of the gate. In this example, the method further includes forming an internal insulating spacer within the gate contact opening that is positioned on and in contact with the exposed portion of the front face, wherein the spacer leaves at least a portion of the upper surface of the gate structure exposed, and forming a conductive gate contact structure (CB) in the conductive gate contact opening.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Lars W. Liebmann, Mark V. Raymond
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Publication number: 20180308752Abstract: Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the dielectric layer. A first conductor layer is conformally deposited with a uniform thickness on the dielectric layer surrounding the first opening. A second conductor layer is formed in a space inside the first opening that is interior of the first conductor layer. The first conductor layer and the second conductor layer collectively define a hybrid feature that is embedded in the dielectric layer.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: Xunyuan Zhang, Frank W. Mont, Sean X. Lin, Mark V. Raymond