Abstract: Methods for controlled segregation of blocks of information encoded in the sequence of a biopolymer, such as nucleic acids and polypeptides, with rapid retrieval based on multiply addressing nanostructured data have been developed. In some embodiments, sequence controlled polymer memory objects include data-encoded biopolymers of any length or form encapsulated by natural or synthetic polymers and including one or more address tags. The sequence address labels are used to associate or select memory objects for sequencing read-out, enabling organization and access of distinct memory objects or subsets of memory objects using Boolean logic. In some embodiments, a memory object is a single-stranded nucleic acid scaffold strand encoding bit stream information that is folded into a nucleic acid nanostructure of arbitrary geometry, including one or more sequence address labels. Methods for controlled degradation of biopolymer-encoded blocks of information in the memory objects are also developed.

Abstract: A system and method for operating multiple security domains on one circuit card assembly, using a field-programmable gate array (FPGA) with an embedded security domain separation gate providing the MAC between multiple soft-core CPUs also embedded in the FPGA. In one embodiment, the FPGA is segregated into two or more security domains with no data paths between soft-core CPUs in each security domain except through the security domain separation gate. The security domain separation gate applies rules to any information to be transmitted between the security domains to avoid transmission of malicious content and to avoid transmission of information of a certain classification level or type to a security domain at a lower classification level or type.

Abstract: A system and method for operating multiple security domains on one circuit card assembly, using a field-programmable gate array (FPGA) with an embedded security domain separation gate providing the MAC between multiple soft-core CPUs also embedded in the FPGA. In one embodiment, the FPGA is segregated into two or more security domains with no data paths between soft-core CPUs in each security domain except through the security domain separation gate. The security domain separation gate applies rules to any information to be transmitted between the security domains to avoid transmission of malicious content and to avoid transmission of information of a certain classification level or type to a security domain at a lower classification level or type.