Abstract: The present invention to be personalized is fitted with a sealed chamber. The chamber is defined by an object and a thin, flexible member. When it is desired to personalize the object, the sealed chamber is filled with uncured paste having predetermined characteristics. The object to be personalized then is brought into contact with a human; thereafter, the paste cures in place to complete the personalizing process.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract: A substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate.

Abstract: A method of forming solder connections on a circuitized substrate having connection pads is provided. A laser ablatable solder mask material, preferably an epoxy, is degassed and then dispensed as a liquid onto the substrate over the circuitization. The surface of the solder mask material as applied is leveled, and the solder mask material is then cured to form a solder mask. Openings are laser ablated in the solder mask material to reveal those connection pads which are to receive solder to form the solder connections. Liquid solder is dispensed under pressure in a confined space into the openings as blades move laterally on top of the solder mask to fill the openings in the solder mask. The solder material is then solidified to form domed solder bumps in the openings.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: A method of forming solder connections on a circuitized substrate having connection pads is provided. A laser ablatable solder mask material, preferably an epoxy, is degassed and then dispensed as a liquid onto the substrate over the circuitization. The surface of the solder mask material as applied is leveled, and the solder mask material is then cured to form a solder mask. Openings are laser ablated in the solder mask material to reveal those connection pads which are to receive solder to form the solder connections. Liquid solder is dispensed under pressure in a confined space into the openings as blades move laterally on top of the solder mask to fill the openings in the solder mask. The solder material is then solidified to form domed solder bumps in the openings.

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract: A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin.

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin.

Abstract: A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract: Selective electrical connections between an electronic component and a test substrate are made using an electrical conductive material. The conductive material of the present invention is a dissolvable material, allowing for rework and repair of a wafer at the wafer-level, and retesting at the wafer-level. In addition, the conductive material may also be used in a permanent package, since the conductive material of the present invention provides complete electrical conductivity and connection between the electronic component and the substrate.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: A method for joining electronic devices such as integrated circuits to vias in a substrate. A solder ball attached to an electronic device is joined to a contact pad of a via by a low melting temperature solder. An opening of a via is plugged to prevent wicking of the low melting temperature solder into the via hole. The opening of the via is plugged using a solder ball or a compressed length of a wire material.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.