Abstract: A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.

Abstract: A microprocessor includes an execution unit for processing a stream of instructions wherein one or more of the instructions reference the eight logical x86 general purpose registers as source and destination registers for operands for the instructions. The microprocessor further includes a register file with a plurality of physical registers in excess of the eight x86 general purpose registers. The physical registers in the register file are mapped to the logical x86 general purpose registers such that one of the physical registers may contain one or more logical source or destination registers of the x86 general purpose registers for an instruction. The register file drives the entire bits of the physical register which contains the destination register for the instruction onto an internal bus. The bits are stored in a latching circuit in the register file. The execution unit performs the instruction and returns the resulting operand to be stored in the logical destination register.

Abstract: A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.

Abstract: A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality of modes which identifies processor state information to output onto the plurality of external pins; and a bus interface unit for communicating data to the external pins of the processor and for detecting an idle bus cycle. The bus interface unit outputs processor state information according to the identified mode onto the plurality of external pins in response to detecting an idle bus cycle.

Abstract: In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages to process instructions for the processor, the processor including a register translation system that controls a renaming of physical registers of the processor to logical registers thereof, a tracking circuit that tracks availability of the physical registers for the renaming, method of operation thereof and processor containing the same.

Abstract: A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicative entry points, thus minimizing the microROM array size.

Abstract: A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.

Abstract: A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.

Abstract: A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an .times.86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The microprocessor's bus interface unit (BIU) includes SCBT logic that generates internal effective BRDY# and the effective KEN# signals from either (a) L2.sub.-- HIT from the L2 cache, or (b) BRDY# or KEN# from the system logic. The effective KEN# signal is used for convert a potentially cacheable read into a burst fill cycle. The exemplary L2 cache is able to perform address decode and cache look-up in time to return L2 HIT to the processor during the ADS# clock with sufficient timing margin to permit the processor to complete the bus transfer (either not burst bus cycle, or the first bus transfer of a burst cycle) in that clock and set up for a next bus transfer in the next clock.

Abstract: A microcomputer has the capacity for executing instructions, requesting prefetches of instructions, and experiencing a change in instruction flow, or a branch. The microcomputer also knows in advance that a change in instruction flow is going to occur. At such time that a branch becomes known there may also be a pending instruction prefetch request. Because a branch is going to occur, there is no need to execute the prefetch. Consequently, the pending instruction prefetch is flushed which thus avoids wasting time making an unnecessary instruction prefetch.

Abstract: A microcomputer prioritizes data operand requests and instruction prefetch requests. Such prioritizing is established by established criteria. The established priority is altered upon the occurrence of a signal. The signal indicates a certain type of data requests. This data request type is deemed to have a higher priority than is typical for a data request. Consequently, in response to receiving the signal which indicates this data request type, the priority is altered so as to be more inclined to perform the data request. This is particularly useful when performing numerous consecutive data operations, such as a co-processor interface operation.