Abstract: Systems and methods for testing components of printed circuit assemblies (PCA) that generate high frequency, low voltage swing signals or that operate using such signals are disclosed. High frequency, low voltage swing signals from the PCA are divided and translated to low frequency signals exhibiting voltage swings compatible with an in-circuit test platform for evaluation. Additionally, high frequency signals exhibiting voltage swings compatible with a PCA are generated. The signals are sent to the PCA for testing components. The division/translation or signal generation/translation logic may be bypassed, enabling the in-circuit test platform and the PCA to send signals between each other even if power to the system is off.

Abstract: Building and testing complex electronic products especially large scale computer systems are handled with control remaining with the owner of the design while a contract manufacturer does the basic manufacturing processes and testing. Nearly all levels of testing are accomplished without sharing high level descriptions of the end product or its features by providing only low level files for test functions. A tester used by the contract manufacturer to exercise the testing function for multiple circuit boards and that tester has numerous features that make it more useful and efficient. The tester has a computer system in it to run the tests using the low level files, and mimics the platform into which the boards will eventually become inserted. Various features provide additional ease of use and functionality.

Abstract: Electronics manufacturers, particularly ones building large scale computer systems, have a need to describe test vectors for third party manufacturers in a low level language description that does not reveal the circuit design to the third party but allows for the third party to build and test the systems, not just with static tests based on BSDL and netlist files, but dynamic tests as well. A conversion process for taking a high level language circuitry description and producing test vectors useable for translation into actual test vectors for testing board-level components of the large scale computer systems is described.

Abstract: Building and testing complex electronic products especially large scale computer systems are handled with control remaining with the owner of the design while a contract manufacturer does the basic manufacturing processes and testing. Nearly all levels of testing are accomplished without sharing high level descriptions of the end product or its features by providing only low level files for test functions. Testing is accomplished without sharing the high level code descriptive of the system design so confidential information is retained. Testing using the low level data is made sufficient to identify what parts need repair despite the lack of high-level information transfer.

Abstract: Apparatus and methods for translating test vectors between a format suitable for use with a standalone integrated circuit tester and a format suitable for use with an in-circuit tester are disclosed. Methods according to the invention include: providing a first test file in a first format that is suitable for use with the standalone integrated circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester. Methods according to the invention also include: providing a first test file in a first format that is suitable for use with the in-circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the standalone integrated circuit tester. Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.

Abstract: The invention provides a method, system, and computer-readable medium having computer-executable instructions for designing a PCB using both HDL design elements and schematic design elements. The inventive method comprises the steps of selecting the HDL design elements and selecting the schematic design elements. The inventive method further comprises automatically interconnecting the HDL design elements, and automatically interconnecting the schematic design elements. The PCB is then physically designed based on the interconnected HDL and schematic design elements. The method may further comprise creating a schematic version from the interconnected HDL design elements, and creating a HDL version from the interconnected schematic design elements. The inventive method also may simulate the schematic version of the HDL design elements, and simulate the HDL version of the schematic design elements.

Abstract: The invention provides a method, system, and computer-readable medium having computer-executable instructions for designing a PCB using both HDL design elements and schematic design elements. The inventive method comprises the steps of selecting the HDL design elements and selecting the schematic design elements. The inventive method further comprises automatically interconnecting the HDL design elements, and automatically interconnecting the schematic design elements. The PCB is then physically designed based on the interconnected HDL and schematic design elements. The method may further comprise creating a schematic version from the interconnected HDL design elements, and creating a HDL version from the interconnected schematic design elements. The inventive method also may simulate the schematic version of the HDL design elements, and simulate the HDL version of the schematic design elements.

Abstract: A method for evaluating a system of interconnected electronic components is disclosed. According to the method, a library element model is generated for each electronic component in the system, in a format that can be input into an ASIC evaluation tool. A system netlist that represents the electronic components and the interconnections between them is generated, also in a format that can be input into an ASIC evaluation tool. The library element models and the system netlist are input into the ASIC evaluation tool, which is used to evaluate the system.

Abstract: A technique for accepting test vectors in one format, generally proven to operate correctly, from an IC tester such as the Logic Master XL2 ("off-bench tester") and processing/converting them into another format for use in a stimulus generator such as the HFS 9009 for bench top testing. The process, which in the exemplary embodiment is implemented in software, accepts various parameters as inputs (e.g., channel name(s) for stimulus generator, range of vectors, etc.) for purposes of extraction and translation. The process provides an Interface and Initialization Unit (IIU) and a Translator Unit (TU). The IIU provides a user interface necessary for a user to select the various options available. In addition, the IIU coordinates the use of memory, file I/O and communication with the active files on the off-bench tester. The IIU verifies user selections and does error checking. Once complete, the TU translates the selected signals for the vector range entered by the user.

Abstract: A quiescent test circuit for interfacing a high precision integrated circuit tester to a device under test (DUT). The quiescent test circuit is capable of supplying a high powered (V1) voltage supply to a DUT while the DUT's desired dynamics internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously which deselects the high-powered (V1) voltage supply to the DUT and selects the integrated circuit tester's parametric measurement unit low power (V4) voltage supply for powering the DUT. The integrated circuit tester, through its parametric measurement unit is capable of precisely measuring the very low quiescent current of the DUT, while powering the DUT.

Abstract: An improved load board design having a generic test circuit integrated into the load board capable of functioning with varying devices under test and requires little to no wiring. The test circuit is located in a fixed and optimal position of the load board with relation to the DUT. In a preferred embodiment, the test circuit is a quiescent test circuit for interfacing an integrated circuit tester to the DUT. The quiescent test circuit is capable of supplying high powered voltage to a DUT while the DUT's desired internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously deselecting the high-powered voltage supply to the DUT and selecting the integrated circuit tester's parametric measurement unit for powering the DUT. The integrated circuit tester, through a parametric measurement unit is capable of measuring the quiescent current of the DUT, while powering the DUT.