Abstract: A memory device includes multiple decoding unit circuitries configured to decode a first set of addressing bits to multiple wordline arming bits each configured to arm a corresponding wordline. Each decoding unit circuitry includes multiple sub-units each configured to decode a second set of addressing bits to a respective subset of the multiple wordline arming bits. The multiple sub-units each include an inverter configured to invert the second set of addressing bits and to output a wordline arming signal. The inverter is coupled between a supply voltage and a common node that is configured to be coupled to and decoupled from a common return by one or more transistors of the wordline decoding circuitry. The multiple-sub-units and each include a bleed transistor that is configured bleed charge onto the wordline arming signal to mitigate for a potential floating condition of the common node.

Abstract: A memory device includes multiple decoding unit circuitries configured to decode a first set of addressing bits to multiple wordline arming bits each configured to arm a corresponding wordline. Each decoding unit circuitry includes multiple sub-units each configured to decode a second set of addressing bits to a respective subset of the multiple wordline arming bits. The multiple sub-units each include an inverter configured to invert the second set of addressing bits and to output a wordline arming signal. The inverter is coupled between a supply voltage and a common node that is configured to be coupled to and decoupled from a common return by one or more transistors of the wordline decoding circuitry. The multiple-sub-units and each include a bleed transistor that is configured bleed charge onto the wordline arming signal to mitigate for a potential floating condition of the common node.