Patents by Inventor Mark W. McDermott

Mark W. McDermott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5926053
    Abstract: A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 20, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Mark W. McDermott, Antone L. Fourcroy
  • Patent number: 5860105
    Abstract: An NDIRTY cache line lookahead technique is used to expedite cache flush and export operations by providing a mechanism to avoid scanning at least some cache lines that do not contain dirty data (and therefore will not have to be exported). The exemplary cache organization uses one-line lookahead where each cache line but the last has associated with it an NDIRTY bit that indicates whether the next cache line contains dirty data. For cache flush and export operations, when a cache line (N) is read to check for dirty data that must be exported, the NDIRTY bit for that cache line is also tested to determine whether the next cache line (N+1) contains dirty data--if the NDIRTY bit is clear, indicating that the next cache line is clean, then that line is skipped and the scan proceeds with the line after that (N+2). This exemplary one-line lookahead implementation is readily extendible to N-line lookahead.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: January 12, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Mark W. McDermott, Robert W. French, Antone L. Fourcroy, Mark E. Burchfield, Xiaoli Y. Mendyke
  • Patent number: 5815692
    Abstract: A processor includes a distributed clock generator employing a plurality of independently adjustable clocks reconstituted locally from multiple signals. A centralized generator is disposed substantially in the middle of the processing system with satellite reconstitutors being disposed around the periphery to service various functional units which collectively manifest the processing system. The distribution of the multiple signals to the satellite reconstitutors provides substantially equal wire length and local reconstitution mitigates R-C time constant skew problems.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: September 29, 1998
    Assignee: National Semiconductor Corporation
    Inventor: Mark W. McDermott
  • Patent number: 5815693
    Abstract: A processing system includes a clock synchromesh that receives indicia of critical activity from various functional units within the processing system and responsive to the indicia, ratchets down/up the frequency of a clock output signal to at least one of the functional units to reduce power consumption. The determination of critical activity is preferably made according to a heuristic internal to a processor under software or hardware control.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: September 29, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Mark W. McDermott, Antone L. Fourcroy
  • Patent number: 5740410
    Abstract: A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation. A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal. 1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks. Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: April 14, 1998
    Assignee: Cyrix Corporation
    Inventor: Mark W. McDermott
  • Patent number: 5734844
    Abstract: Bidirectional handshake protocol circuitry is provided for asserting and deasserting a signal across a single line between a first device and a second device. Only the first device is permitted to assert the signal on the single line; and only the second device is permitted to deassert the signal on the single line. The protocol is particularly useful between a chipset and a CPU where the chipset asserts a System Management Interrupt (SMI) and the CPU deasserts the interrupt to signal to the chipset that the service routine is complete. After assertion (or deassertion), there is an overlap or hand-off period whereby the single line is driven in the same direction by both devices. After a predetermined number of clock cycles, the device which asserted or deasserted the signal is tristated to await deassertion or assertion, respectively.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: March 31, 1998
    Assignee: Cyrix Corporation
    Inventors: Claude Moughanni, Mark W. McDermott
  • Patent number: 5734881
    Abstract: A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: March 31, 1998
    Assignee: Cyrix Corporation
    Inventors: Christopher E. White, Antone L. Fourcroy, Mark W. McDermott
  • Patent number: 5592107
    Abstract: A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: January 7, 1997
    Assignee: Cyrix Corporation
    Inventors: Mark W. McDermott, John E. Turner
  • Patent number: 5568067
    Abstract: A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: October 22, 1996
    Assignee: Cyrix Corporation
    Inventors: Mark W. McDermott, John E. Turner
  • Patent number: 5448744
    Abstract: An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset.
    Type: Grant
    Filed: November 6, 1989
    Date of Patent: September 5, 1995
    Assignee: Motorola, Inc.
    Inventors: James B. Eifert, John J. Vaglica, James C. Smallwood, Mark W. McDermott, Hiroyuki Sugiyama, William P. LaViolette, Bradley G. Burgess
  • Patent number: 5402458
    Abstract: Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: March 28, 1995
    Assignee: Cyrix Corporation
    Inventors: Claude Moughanni, Mark W. McDermott
  • Patent number: 5361392
    Abstract: A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: November 1, 1994
    Assignee: Motorola, Inc.
    Inventors: Antone L. Fourcroy, Mark W. McDermott, John P. Dunn, Bradley G. Burgess
  • Patent number: 5233314
    Abstract: A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: August 3, 1993
    Assignee: Cyrix Corporation
    Inventors: Mark W. McDermott, Richard B. Reis
  • Patent number: 5157781
    Abstract: A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.
    Type: Grant
    Filed: January 2, 1990
    Date of Patent: October 20, 1992
    Assignee: Motorola, Inc.
    Inventors: Wallace B. Harwood, Mark W. McDermott, Dennis K. Verbeek
  • Patent number: 5138709
    Abstract: In a microprocessor system including arbitration for an interrupt, an apparatus and method for monitoring the arbitration lines to determine whether an interrupt request is real or spurious is includued. Once an interrupt acknowledge signal is provided, the interrupting apparatus must arbitrate for the interrupt slot. If no arbitration occurs the interrupt request was spurious and bus error is activated.
    Type: Grant
    Filed: April 11, 1990
    Date of Patent: August 11, 1992
    Assignee: Motorola, Inc.
    Inventors: Randall L. Jones, Mark R. Heene, Mark W. McDermott
  • Patent number: 5029272
    Abstract: An input/output circuit of an integrated circuit with a programmable input sensing time. The output driver of the input/output circuit is open drain and is designed for use in a wire-OR configuration with other devices. The input/output circuit is coupled to a bonding pad and through the bonding pad to a device pin, and counts a programmable number of clock cycles between a negation of an output drive signal and when the state of the pin is sampled as an input. Since different applications use a wide range of values for external pullup resistors, the input/output circuit allows adjustment of the sample time to fit a particular application.
    Type: Grant
    Filed: November 3, 1989
    Date of Patent: July 2, 1991
    Assignee: Motorola, Inc.
    Inventors: Antone L. Fourcroy, Mark W. McDermott, James C. Smallwood
  • Patent number: 4959561
    Abstract: An output buffer with reduced supply line disturbance is provided for use in high performance microprocessor circuits. The output buffer uses a resistor and transistor as a sensing circuit, in parallel with an output driver transistor, thereby providing a negative feedback path into the control circuitry for the output driver. The sensing circuit detects the strength of the output driver transistor, by monitoring the amount of capacitance on the output node when the output buffer is driving the output signal to a logic high or logic low state, and rapidly produces a control voltage. The current flowing through the driver transistor and the sensor transistor causes a voltage drop across the resistor, which is fedback into the control circuitry. The control voltage is fed back into the output buffer control circuitry, thereby facilitating the reduction of the current drive capabilities of the driver and sensor transistors.
    Type: Grant
    Filed: March 26, 1990
    Date of Patent: September 25, 1990
    Assignee: Motorola, Inc.
    Inventors: Mark W. McDermott, Ernest A. Carter
  • Patent number: 4931748
    Abstract: A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.
    Type: Grant
    Filed: June 9, 1989
    Date of Patent: June 5, 1990
    Assignee: Motorola, Inc.
    Inventors: Mark W. McDermott, Antone L. Fourcroy
  • Patent number: 4366560
    Abstract: A circuit for detecting power supply variations in which a first and second transistor are connected in a cross-coupled mode. A load device is connected to each transistor and to a source of power. The loads are unbalanced such that upon application of power to the circuit a first state is always assumed. The cell is forced to its second state. A charge transfer device is connected between first and second nodes formed at the connection between the first transistor and its load and the second transistor and its load. Upon reduction of power supply voltage below that of the active node, a charge transfer takes place which allows the cell to return to its initial state. Detection of the initial state indicates loss or reduction of power has occurred.
    Type: Grant
    Filed: September 22, 1980
    Date of Patent: December 28, 1982
    Assignee: Motorola, Inc.
    Inventors: Mark W. McDermott, Neil B. Feldman