Patents by Inventor Mark W. Randolph
Mark W. Randolph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9196624Abstract: Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.Type: GrantFiled: July 10, 2012Date of Patent: November 24, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Bradley Marc Davis, Mark W. Randolph, Sung-Yong Chung, Hidehiko Shiraiwa
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Publication number: 20150103601Abstract: Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: Spansion LLCInventors: Gulzar A. KATHAWALA, Mark W. RANDOLPH, Yi HE, Zhizheng LIU, Tio Wei NEO, Cindy SUN, Shivananda SHETTY, Phuog BANH, Richard FASTOW, Loi LA, Harry Hao KUO
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Patent number: 8995198Abstract: Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.Type: GrantFiled: October 10, 2013Date of Patent: March 31, 2015Assignee: Spansion LLCInventors: Gulzar A. Kathawala, Mark W. Randolph, Yi He, Zhizheng Liu, Tio Wei Neo, Cindy Sun, Shivananda Shetty, Phuong Banh, Richard Fastow, Loi La, Harry Hao Kuo
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Patent number: 8957472Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.Type: GrantFiled: January 24, 2012Date of Patent: February 17, 2015Assignee: Spansion LLCInventors: Ashot Melik-Martirosian, Mark T. Ramsbey, Mark W. Randolph
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Patent number: 8938655Abstract: Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.Type: GrantFiled: December 20, 2007Date of Patent: January 20, 2015Assignee: Spansion LLCInventors: Darlene G. Hamilton, Mark W. Randolph, Don Carlos Darling, Ron Kornitz
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Publication number: 20140015138Abstract: Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: SPANSION LLCInventors: Bradley Marc DAVIS, Mark W. Randolph, Sung-Yong Chung, Hidehiko Shiraiwa
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Publication number: 20120122285Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Inventors: Ashot Melik-Martirosian, Mark T. Ramsbey, Mark W. Randolph
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Patent number: 8125018Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.Type: GrantFiled: January 12, 2005Date of Patent: February 28, 2012Assignee: Spansion LLCInventors: Ashot Melik-Martirosian, Mark T. Ramsbey, Mark W. Randolph
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Patent number: 7995386Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.Type: GrantFiled: November 21, 2008Date of Patent: August 9, 2011Assignee: Spansion LLCInventors: Yuji Mizuguchi, Mark W. Randolph, Darlene Gay Hamilton, Yi He, Zhizheng Liu, Yanxia (Emma) Lin, Xianmin Yi, Gulzar Kathawala, Amol Ramesh Joshi, Kuo-Tung Chang, Edward Franklin Runnion, Sung-Chul Lee, Sung-Yong Chung, Yanxiang Liu, Yu Sun
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Patent number: 7944746Abstract: Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.Type: GrantFiled: November 27, 2007Date of Patent: May 17, 2011Assignee: Spansion LLCInventors: Gwyn Robert Jones, Mark W Randolph, John Darilek, Sean O'Mullan, Jacob Marcantel, Rick Anundson, Adam Shackleton, Xiaojian Chu, Abhijit Raghunathan, Asif Arfi, Gulzar Ahmed Kathawala, Zhizheng Liu, Sung-Chul Lee
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Publication number: 20100128521Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Applicant: SPANSION LLCInventors: Yuji Mizuguchi, Mark W. Randolph, Darlene Gay Hamilton, Yi He, Zhizheng Liu, Yanxia (Emma) Lin, Xianmin Yi, Gulzar Kathawala, Amol Ramesh Joshi, Kuo-Tung Chang, Edward Franklin Runnion, Sung-Chul Lee, Sung-Yong Chung, Yanxiang Liu, Yu Sun
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Publication number: 20090161466Abstract: Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: SPANSION LLCInventors: Darlene G. Hamilton, Mark W. Randolph, Don Carlos Darling, Ron Kornitz
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Publication number: 20090135659Abstract: Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles.Type: ApplicationFiled: November 27, 2007Publication date: May 28, 2009Applicant: SPANSION LLCInventors: Gwyn Robert Jones, Mark W. Randolph, John Darilek, Sean O'Mullan, Jacob Marcantel, Rick Anundson, Adam Shackleton, Xiaojian Chu, Abhijit Raghunathan, Asif Arfi, Gulzar Ahmed Kathawala, Zhizheng Liu, Sung-Chul Lee
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Patent number: 7125763Abstract: A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline.Type: GrantFiled: June 19, 2001Date of Patent: October 24, 2006Assignee: Spansion LLCInventors: Daniel Sobek, Timothy J. Thurgate, Mark W. Randolph
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Patent number: 7001807Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.Type: GrantFiled: November 24, 2004Date of Patent: February 21, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Wei Zheng, Mark W. Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey
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Patent number: 6967873Abstract: A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.Type: GrantFiled: October 2, 2003Date of Patent: November 22, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Darlene G. Hamilton, Zhizheng Liu, Mark W. Randolph, Yi He, Edward Hsia, Kulachet Tanpairoj, Mimi Lee, Alykhan Madhani
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Patent number: 6965143Abstract: A memory cell with reduced short channel effects is described. A source region and a drain region are formed in a semiconductor substrate. A trench region is formed between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A gate dielectric layer is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer.Type: GrantFiled: October 10, 2003Date of Patent: November 15, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Wei Zheng, Mark W. Randolph
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Patent number: 6958272Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.Type: GrantFiled: January 12, 2004Date of Patent: October 25, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Emmanuil H. Lingunis, Nga-Ching Alan Wong, Sameer Haddad, Mark W. Randolph, Mark T. Ramsbey, Ashot Melik-Martirosian, Edward F. Runnion, Yi He
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Patent number: 6911704Abstract: A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.Type: GrantFiled: October 14, 2003Date of Patent: June 28, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Mark W. Randolph, Sameer S. Haddad, Timothy Thurgate, Richard Fastow
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Patent number: 6906959Abstract: The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.Type: GrantFiled: November 27, 2002Date of Patent: June 14, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Mark W. Randolph, Chi Chang, Yi He, Wei Zheng, Edward F. Runnion, Zhizheng Liu