Patents by Inventor Mark W. Redekopp

Mark W. Redekopp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Complex layout-based topological data analysis of analog netlists to extract hierarchy and functionality
    Patent number: 9367659
    Abstract: A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: June 14, 2016
    Assignee: Raytheon Company
    Inventors: Parviz Saghizadeh, Thomas Allen Spargo, Robert T. Narumi, Mark W. Redekopp
  • REVERSE SYNTHESIS OF DIGITAL NETLISTS
    Publication number: 20150100929
    Abstract: A method and method of extracting information from a netlist. The netlist for a device under test (DUT) is read and a circuit selected to be transformed. Transformation candidates are identified using transformation specific criteria and verification methods are applied to prove the transformation is equivalent to the circuit being transformed. If the candidate transformation is equivalent to the circuit being transformed, the system commits to the transformation. If the candidate transformation is not equivalent to the circuit being transformed, the transformation is undone.
    Type: Application
    Filed: August 7, 2014
    Publication date: April 9, 2015
    Inventors: Mark W. Redekopp, Parviz Saghizadeh
  • COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY
    Publication number: 20150100928
    Abstract: A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.
    Type: Application
    Filed: August 7, 2014
    Publication date: April 9, 2015
    Inventors: Parviz Saghizadeh, Thomas Allen Spargo, Robert T. Narumi, Mark W. Redekopp
  • Systems and methods for mapping state elements of digital circuits for equivalence verification
    Patent number: 8407639
    Abstract: Systems and methods for mapping state elements of digital circuits for equivalence verification are provided.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: March 26, 2013
    Assignee: Raytheon Company
    Inventor: Mark W. Redekopp
  • SYSTEMS AND METHODS FOR MAPPING STATE ELEMENTS OF DIGITAL CIRCUITS FOR EQUIVALENCE VERIFICATION
    Publication number: 20120198402
    Abstract: Systems and methods for mapping state elements of digital circuits for equivalence verification are provided.
    Type: Application
    Filed: January 27, 2011
    Publication date: August 2, 2012
    Inventor: Mark W. Redekopp