Abstract: A capacitive sense array configured to improve noise immunity in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements disposed in straight parallel lines along a first axis of the capacitive sense array. A second set of sense elements is disposed in crooked paths about a second axis of the capacitive sense array. The first and second sets form a capacitive sense array that includes crooked sense paths in at least one of the axes of the sense array.

Abstract: A capacitive sense array configured to improve noise immunity in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements disposed in straight parallel lines along a first axis of the capacitive sense array. A second set of sense elements is disposed in crooked paths about a second axis of the capacitive sense array. The first and second sets form a capacitive sense array that includes crooked sense paths in at least one of the axes of the sense array.

Abstract: A method and apparatus for verifying non-volatile memory. A first transmission of data is received by a first memory of a device. The data is received by a non-volatile memory of the device. The data received by the non-volatile memory is verified by comparing it to the data in the first memory with comparison logic of the device. The verification is performed without receiving a second transmission of the data and without sending a second transmission of the data. A result is generated from the comparison.

Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

Abstract: An apparatus comprising a storage element coupled between a first and a second bond pad, the storage element having a physical characteristic that can be measured and altered. Data may be stored in the storage element by altering the physical characteristic.