Patents by Inventor Mark W. Stephenson
Mark W. Stephenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10296639Abstract: Each of a plurality of stations has a respective sequence of tracks of Internet content of common subject matter and a respective play pointer indicating a location in the sequence of tracks. In response to a first input, the presentation mode of the station is configured in a continuous play mode in which the play pointer is progressed through the sequence of tracks queued to the station regardless of whether or not the station is presently selected for presentation. In response to a second input, the presentation mode is configured in a pause play mode in which the play pointer is progressed through the sequence of tracks queued to the station only while the station is selected for presentation to a user and otherwise pauses progression of the play pointer. The processor transmits tracks of the station and progresses the play pointer in accordance with the configured presentation mode.Type: GrantFiled: September 5, 2013Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Patrick J. Bohrer, Michael D. Kistler, Ramakrishnan Rajamony, Mark W. Stephenson
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Patent number: 9946550Abstract: A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.Type: GrantFiled: September 17, 2007Date of Patent: April 17, 2018Assignee: International Business Machines CorporationInventors: Ram Rangan, William E. Speight, Mark W. Stephenson, Lixin Zhang
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Patent number: 9431004Abstract: A respective sequence of tracks of Internet content of common subject matter is queued to each of a plurality of stations, where each of the tracks of Internet content resides on a respective Internet resource in textual form. In response to receiving a sample input, snippets of each of multiple tracks queued to a selected station among the plurality of stations is transmitted for audible presentation as synthesized human speech, where each of the snippets includes only a subset of a corresponding track. Thereafter, one or more complete tracks among the multiple tracks for which snippets were previously transmitted are transmitted for audio presentation as synthesized human speech.Type: GrantFiled: September 5, 2013Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Patrick J. Bohrer, Michael D. Kistler, Ramakrishnan Rajamony, Mark W. Stephenson
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Patent number: 9262140Abstract: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.Type: GrantFiled: May 19, 2008Date of Patent: February 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ram Rangan, Mark W. Stephenson, Lixin Zhang
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Publication number: 20150066510Abstract: A respective sequence of tracks of Internet content of common subject matter is queued to each of a plurality of stations, where each of the tracks of Internet content resides on a respective Internet resource in textual form. In response to receiving a sample input, snippets of each of multiple tracks queued to a selected station among the plurality of stations is transmitted for audible presentation as synthesized human speech, where each of the snippets includes only a subset of a corresponding track. Thereafter, one or more complete tracks among the multiple tracks for which snippets were previously transmitted are transmitted for audio presentation as synthesized human speech.Type: ApplicationFiled: September 5, 2013Publication date: March 5, 2015Inventors: PATRICK J. BOHRER, MICHAEL D. KISTLER, RAMAKRISHNAN RAJAMONY, MARK W. STEPHENSON
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Publication number: 20150067507Abstract: Each of a plurality of stations has a respective sequence of tracks of Internet content of common subject matter and a respective play pointer indicating a location in the sequence of tracks. In response to a first input, the presentation mode of the station is configured in a continuous play mode in which the play pointer is progressed through the sequence of tracks queued to the station regardless of whether or not the station is presently selected for presentation. In response to a second input, the presentation mode is configured in a pause play mode in which the play pointer is progressed through the sequence of tracks queued to the station only while the station is selected for presentation to a user and otherwise pauses progression of the play pointer. The processor transmits tracks of the station and progresses the play pointer in accordance with the configured presentation mode.Type: ApplicationFiled: September 5, 2013Publication date: March 5, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: PATRICK J. BOHRER, MICHAEL D. KISTLER, RAMAKRISHNAN RAJAMONY, MARK W. STEPHENSON
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Patent number: 8589895Abstract: A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.Type: GrantFiled: January 13, 2010Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Elmootazbellah N. Elnozahy, Mark W. Stephenson
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Patent number: 8453129Abstract: A method, computer system, and computer program product for using one or more hardware interrupts to drive dynamic binary code recompilation. The execution of a plurality of instructions is monitored to detect a problematic instruction. In response to detecting the problematic instruction, a hardware interrupt is thrown to a dynamic interrupt handler. A determination is made whether a threshold for dynamic binary code recompilation is satisfied. If the threshold for dynamic code recompilation is satisfied, the dynamic interrupt handler optimizes at least one of the plurality of instructions.Type: GrantFiled: April 24, 2008Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Mark W. Stephenson, Ram Rangan
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Publication number: 20110173592Abstract: A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.Type: ApplicationFiled: January 13, 2010Publication date: July 14, 2011Applicant: International Business Machines CorporationInventors: Elmootazbellah N. Elnozahy, Mark W. Stephenson
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Patent number: 7886132Abstract: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.Type: GrantFiled: May 19, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Ram Rangan, Mark W. Stephenson, Lixin Zhang
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Publication number: 20090287908Abstract: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.Type: ApplicationFiled: May 19, 2008Publication date: November 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ram Rangan, Mark W. Stephenson, Lixin Zhang
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Publication number: 20090288063Abstract: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.Type: ApplicationFiled: May 19, 2008Publication date: November 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ram Rangan, Mark W. Stephenson, Lixin Zhang
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Publication number: 20090271772Abstract: A method, computer system, and computer program product for using one or more hardware interrupts to drive dynamic binary code recompilation. The execution of a plurality of instructions is monitored to detect a problematic instruction. In response to detecting the problematic instruction, a hardware interrupt is thrown to a dynamic interrupt handler. A determination is made whether a threshold for dynamic binary code recompilation is satisfied. If the threshold for dynamic code recompilation is satisfied, the dynamic interrupt handler optimizes at least one of the plurality of instructions.Type: ApplicationFiled: April 24, 2008Publication date: October 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark W. Stephenson, Ram Rangan
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Publication number: 20090077354Abstract: A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.Type: ApplicationFiled: September 17, 2007Publication date: March 19, 2009Inventors: Ram Rangan, William E. Speight, Mark W. Stephenson, Lixin Zhang