Abstract: A vehicle having a vehicle sensor configured to detect a vehicle state; an actuatable spoiler moveable into a deployed position and a stowed position; an actuator operable to move the actuatable spoiler into the deployed position and the stowed position; and a controller configured to selectively instruct the actuator to actively cycle the actuatable spoiler between the deployed position and the stowed position based on the detected vehicle state. The actuatable spoiler is retained in the deployed position for a longer length of time than in the stowed position. The vehicle also includes a human machine interface selectively actuated by an operator of the vehicle to retain the actuatable spoiler in the stowed position for a predetermined length of time.

Abstract: A vehicle having a vehicle sensor configured to detect a vehicle state; an actuatable spoiler moveable into a deployed position and a stowed position; an actuator operable to move the actuatable spoiler into the deployed position and the stowed position; and a controller configured to selectively instruct the actuator to actively cycle the actuatable spoiler between the deployed position and the stowed position based on the detected vehicle state. The actuatable spoiler is retained in the deployed position for a longer length of time than in the stowed position. The vehicle also includes a human machine interface selectively actuated by an operator of the vehicle to retain the actuatable spoiler in the stowed position for a predetermined length of time.

Abstract: A rear wheelhouse vent assembly and a vehicle include a wheelhouse liner. A first edge of the wheelhouse liner defines a cutout that is open along the first edge. The assembly includes a side panel and a duct. The side panel defines a recess, and the wheelhouse liner is disposed along the recess transverse to the side panel to define an open area. The duct is disposed in the cutout. The duct includes a first wall, a second wall and a third wall. The second wall is disposed between the first and third walls. The first and third walls each extend outwardly away from the second wall to respective distal ends to space the second wall from an inner surface of the side panel. The duct is secured to the inner surface and presents a tunnel that vents the open area.

Abstract: A pass transistor signal level translator between a first voltage level and a higher second voltage level having a bias circuit for the pass transistor including a first switching circuit coupled to the first voltage level for providing a bias voltage that is less than the first voltage level. A second switching circuit is coupled to the second voltage level for providing a pulse at substantially the second voltage to the bias voltage. A voltage clamping circuit is coupled between the bias voltage and a reference voltage.

Abstract: A transition detect circuit includes: a first input port referenced to a first supply voltage node and a second input port referenced to a second supply voltage node. The circuit simultaneously monitors both ports for transitions, and once a transition occurs, directly generates the translated control signals at its output. Once a transition occurs at the inputs, the translated control signal is generated at the output within at most two gate delays. The circuit has very low quiescent current.

Abstract: The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to a control node of the second high side output device; a high side one-shot device having an output coupled to a first input of the first logic gate; a low side one-shot device having an output coupled to a first input of the second logic gate; and a feedback device coupled between the output node and a second input of the first logic gate, and between the output node and a second input of the second logic gate, and between the output node and the input to the high side resistor bypass device, and between the output node and the input to the low side one-shot resistor bypass device.

Abstract: A pass transistor signal level translator between a first voltage level and a higher second voltage level having a bias circuit for the pass transistor including a first switching circuit coupled to the first voltage level for providing a bias voltage that is less than the first voltage level. A second switching circuit is coupled to the second voltage level for providing a pulse at substantially the second voltage to the bias voltage. A voltage clamping circuit is coupled between the bias voltage and a reference voltage.

Abstract: A blocking circuit technique achieves very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance. The blocking circuit employs a diode-connected P-channel device in parallel with a PN diode. The diode-connected P-channel device provides enough forward leakage in the subthreshold region to keep Ioz through the upper output driver to a very low level (0.2 uA typical). Further, both the diode-connected P-channel device and the PN diode together provide enough reverse blocking capability to keep Ioff to a very low level (0.2 uA typical).