Abstract: Methods for transfer of bulk data from a leader device to a follower device over a bus are described. The methods employ address frames and write frames. The bus, the address frames, and the write frames are compatible with Clause 45 of IEEE Std 802.3-2015. The methods achieve a reduction in the number of frames employed to transfer data as contrasted with conventional indirect write transactions. After transmitting on a Management Data Input/Output (MDIO) data signal an address frame that specifies the follower device and that contains the address of an initial register, the leader device proceeds to transmit on the MDIO data signal multiple write frames that specify the target follower device, the multiple write frames transmitted one at a time, each write frame containing a different block of the bulk data. A follower device implements a post-write-increment-address action, despite the absence of any definition in Clause 45 of IEEE Std 802.3-2015 of a post-write-increment-address frame.

Abstract: Methods for transfer of bulk data from a leader device to a follower device over a bus are described. The methods employ address frames and write frames. The bus, the address frames, and the write frames are compatible with Clause 45 of IEEE Std 802.3-2015. The methods achieve a reduction in the number of frames employed to transfer data as contrasted with conventional indirect write transactions. After transmitting on a Management Data Input/Output (MDIO) data signal an address frame that specifies the follower device and that contains the address of an initial register, the leader device proceeds to transmit on the MDIO data signal multiple write frames that specify the target follower device, the multiple write frames transmitted one at a time, each write frame containing a different block of the bulk data. A follower device implements a post-write-increment-address action, despite the absence of any definition in Clause 45 of IEEE Std 802.3-2015 of a post-write-increment-address frame.

Abstract: A chip includes a pool of blocks. Each block is adapted to implement a communication protocol. A cross-connect configurably connects between the blocks. A configured connection through the cross-connect between a sending block and a receiving block includes a lane with a toggle line and multiple data lines. The receiving block uses the toggle line to determine when valid data is on the data lines. The sending block and receiving block are on different clock domains.

Abstract: At a generator, frame events are received indicative of frame boundaries. The amount of client data received between frame events is counted to get a raw count. The raw count is low-pass filtered to get a smoothed value. At a receiver, an indication of the smoothed count is received from the generator; and the indication is smoothed using a low-pass filter and used to produce a client data rate.

Abstract: A method and system for conveying an arbitrary mixture of high and low latency traffic streams across a common switch fabric implements a multi-dimensional traffic classification scheme, in which multiple orthogonal traffic classification methods are successively implemented for each traffic stream traversing the system. At least two diverse paths are mapped through the switch fabric, each path being optimized to satisfy respective different latency requirements. A latency classifier is adapted to route each traffic stream to a selected path optimized to satisfy latency requirements most closely matching a respective latency requirement of the traffic stream. A prioritization classifier independently prioritizes traffic streams in each path. A fairness classifier at an egress of each path can be used to enforce fairness between responsive and non-responsive traffic streams in each path.

Abstract: A method and system for conveying an arbitrary mixture of high and low latency traffic streams across a common switch fabric implements a multi-dimensional traffic classification scheme, in which multiple orthogonal traffic classification methods are successively implemented for each traffic stream traversing the system. At least two diverse paths are mapped through the switch fabric, each path being optimized to satisfy respective different latency requirements. A latency classifier is adapted to route each traffic stream to a selected path optimized to satisfy latency requirements most closely matching a respective latency requirement of the traffic stream. A prioritization classifier independently prioritizes traffic streams in each path. A fairness classifier at an egress of each path can be used to enforce fairness between responsive and non-responsive traffic streams in each path.