Patents by Inventor Mark William Baumann

Mark William Baumann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8890332
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark William Baumann, Richard S. Roy
  • Publication number: 20130313723
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Application
    Filed: March 15, 2013
    Publication date: November 28, 2013
    Applicant: MOSYS, INC.
    Inventors: Michael J. Miller, Mark William Baumann, Richard S. Roy
  • Patent number: 8368217
    Abstract: A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: February 5, 2013
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark William Baumann, Richard S. Roy