Abstract: A method and apparatus for line card redundancy in a communication switch is presented. The switch includes an arbiter coupled to the input of a switch core and a line card pair. The first line card of the line card pair is considered an active line card, whereas the second line card of the line card pair is considered the redundant, or inactive, line card. The active and inactive line cards are determined based on selection information received by the arbiter. Based on the selection information, the arbiter preferentially provides ingress data from the active line card to the corresponding input of the switch core. A router is coupled to the line card pair and to an output of the switch core. The router passes egress data from the switch core to at least one of the first and second line cards based on routing information included in the egress data.

Abstract: Methods and devices for scheduling data transmission processing based on the size of the data transmission unit and a predetermined increment value. A scheduler has slots which represent specific amounts of time in which a queue of data transmission units to be processed is represented. An indicator determines which slot and thereby which queue is being examined. Each queue is assigned a specific increment value and each data transmission unit in a queue is assigned a count value based on the size of the data transmission unit. When a data transmission unit is at the head of the queue and is a candidate for processing, if the count value is greater than a predetermined value then the queue and thereby the data transmission unit at the head of the queue is rescheduled at a later time. This is effected by assigning the queue to a subsequent slot in the scheduler. The subsequent slot in the scheduler is determined based on the given increment value for that queue.

Abstract: Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size.

Abstract: Methods and devices for scheduling data transmission processing based on the size of the data transmission unit and a predetermined increment value. A scheduler has slots which represent specific amounts of time in which a queue of data transmission units to be processed is represented. An indicator determines which slot and thereby which queue is being examined. Each queue is assigned a specific increment value and each data transmission unit in a queue is assigned a count value based on the size of the data transmission unit. When a data transmission unit is at the head of the queue and is a candidate for processing, if the count value is greater than a predetermined value then the queue and thereby the data transmission unit at the head of the queue is rescheduled at a later time. This is effected by assigning the queue to a subsequent slot in the scheduler. The subsequent slot in the scheduler is determined based on the given increment value for that queue.

Abstract: Methods and devices for dividing differently sized data transmission units into fixed sized segments for use with a switch core. Differently sized data transmission units are divided into a number of fixed size segments. Each of the fixed size segments has a segment header section and segment payload section. The segment header section has routing information for the segments and a field for indicating whether the segment payload section is fully occupied or not. The segment payload section carries the actual data from the data transmission unit that has been divided. If the segment payload section is not fully occupied, a field in the payload section indicates how much of the space in the segment payload section is occupied. To track segments from the same data transmission unit the segment header section also has a EOP or end of package field that indicates whether a segment the end of the sequence of segments derived from a single divided data transmission unit.

Abstract: A congestion management system that controls access to any shared resource by incoming data transmission units. The access can be controlled based on the particular connection associated with a data transmission unit. Every shared resource, such as a pool of buffer memory, is represented by a partition. The congestion management system is comprised of a plurality of connection data structures and a plurality of partition data structures. Each connection data structure represents a particular connection and, similarly, each partition data structure represents a particular partition. Each incoming DTU is associated with a single connection but may be allowed access to more than one partition. Each partition is associated with a shared resource and access to each partition is governed by the state of a partition data structure. If a partition data structure indicates that a specific threshold has been met, then access to the shared resource by other DTUs is denied.

Abstract: A method and apparatus is for buffering data cells in a queuing element is presented. Each queuing element includes a partitioned buffer, where the partitioned buffer includes a plurality of partitions. Each of the partitions stores data cells received by the queuing element. Storage of the data cells into the partitions is accomplished by using an array of logical queues. Each logical queue of the array of logical queues maps data cells corresponding to that logical queue to a particular partition of the plurality of partitions. More than one logical queue may map data cells to a particular partition. Each partition may include a reserved portion, where each logical queue that maps to the partition may map a portion of its data cells to the reserved portion. The resources of the reserved portion to which a logical queue maps data cells are reserved to that specific logical queue and cannot be utilized by other logical queues.

Abstract: A method and apparatus for a high bandwidth multi-source interconnection using point-to-point buses that may be utilized in a communication switch is presented. In the communication switch, a number of output buffers are included to correspond to the outputs of the switch. Each output receives data from a number of different inputs to the switch. Each output buffer includes a plurality of queuing elements where each queuing element receives data from at least one of the inputs and buffers the data prior to insertion into an output data stream corresponding to the output of the output buffer. The plurality of queuing of elements are intercoupled in a daisy chain configuration such that a daisy chain output of one queuing element is coupled to the daisy chain input of the succeeding queuing element. The daisy chain configuration provides a data path through which a data stream that becomes the output of the output buffer is carried.

Abstract: Systems and methods for data traffic management in a node in a data network. A data path element receives data packets from the network and receives instructions from a buffer management element, coupled to the data path element, whether specific data packets are to be accepted for buffering or not. This decision is based on the status of a buffer memory bank coupled to the data path element. If a data packet is accepted, a data unit descriptor for that packet is queued for processing by a scheduler element coupled to the data path element. The scheduler element determines when a specific data packet is to be dispatched from the buffer memory bank based on the queued data unit descriptor.

Abstract: Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size.