Abstract: A data processing system, and a method of operating a data processing system. The data processing system comprises a clock generator for generating a system clock signal, and a memory unit having a plurality of memory modules for storing data. The data processing system further comprises a memory controller coupled to the clock generator for receiving the system clock signal therefrom, and coupled to the memory modules for outputting memory address and control signals to said modules. The memory controller is programmable to have different clock-to-output delays, on signals from the memory controller end, based on the memory installed in the system.

Abstract: A memory module comprising: a plurality of memory devices associated with the module; each of the memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; the logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with the address inputs and bank address input signals corresponding to N bank memory devices; the logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device or at least one of the bank address signals to a different device bank address.

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller. The system checks the first logic to see if the mode is compatible with the system mode. If not, different PD data is written to and read from the third logic successively until a compatible mode is found or the available PD data is exhausted.

Abstract: A memory module comprising: a plurality of memory devices associated with the module; each of said memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address input signals corresponding to N bank memory devices; said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device or at least one of said bank address signals to a different device bank address.

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller.

Abstract: A memory module comprising: a plurality of memory devices associated with the module; each of said memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address input signals corresponding to N bank memory devices; said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device.

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller.

Abstract: A packaging assembly for semiconductor memory modules using synchronous clocking signals distributed to each module within a package. The clock distribution network on the assembly is characterized by including a transmission line termination means, preferably a resistor, coupled immediately adjacent to one of the assembly input pins.

Abstract: A memory module configured such that it can be operated as a first memory module such as a (Single In-line Memory Module) SIMM or as a second memory module such as a (Dual In-linc Memory Module) DIMM module without requiring external switching circuitry. This is accomplished by providing a memory module card with a circuit thereon that is designed to emulate a DIMM module when plugged into a DIMM socket as found in the latest computer architectures and to emulate a SIMM module when plugged into a SIMM socket as found in older computer architectures. The memory module is provided with memory devices (DRAMS or SDRAMS) and interconnecting bypass devices (CMOS transistor pairs) mounted thereon.

Abstract: A printed circuit card having first and second circuit units mounted thereon in connection to terminal pads adjacent two card edges, with the first and second circuit units being in connection to each other and to select pads of a first edge such that upon insertion of that edge into a given card socket, both circuit units are enabled, and the circuit units also being in connection to the pads of a second edge such that upon insertion of that edge into a second card socket, only the second circuit unit is enabled. In the preferred embodiment, the card is a memory module card having buffer and memory circuit units designed to cooperate with each other and with either of standard, buffered or unbuffered memory card sockets in a system board in accordance with insertion of a first or second pad edge in one of the card sockets to automatically provide, either combined circuit unit operation, or single circuit operation. The invention is also applicable to clocked register circuits and series pass devices.

Abstract: According to the present invention, a computer system and method of operation of the system is provided wherein the computer system has a memory controller which generates first and second RAS signals and Y rows of addresses in memory, and wherein the memory of the system, either as a planar or add-on memory, is configured with Y+1 rows of addresses operable by a single RAS. The system includes logic, preferably which is on an ASIC chip, to convert one of the RAS signals from the memory controller to the high order address bit for the memory rows, thus constituting Y+1 rows of addressable space. The logic also generates a master RAS signal when either RAS generated by the memory controller goes active. The logic also provides for a refresh operation of all of the memory locations during a RAS only refresh operation. This is preferably controlled by a counter in the logic circuit which assures that each row gets refreshed in order when both RASes go LOW for a refresh cycle.

Abstract: Reduced specification DRAMs are used in memory assemblies in such a way as to maximize the use of the good cells in the reduced specification DRAM chips. An external memory array is mapped to replace defective memory locations on a real time basis. The major components are (1) a non-volatile storage device, (2) a logic device, and (3) a volatile storage device. The non-volatile storage device, such as an EPROM, EEPROM, or a flash memory chip, is used to retain address information for all memory fails on a given assembly. In simpler implementations, the use of specific combinations of RAM failure types can be used in addition to a logic decode chip, with the raw card identifying to the decode chip the failing address information (via solder jumpers). The logic device is an ASIC or programmable logic device which contains the bit steering logic and timing generation logic to redirect defective RAM addresses to an alternate storage device for all read and write operations.

Abstract: A vital product data (VPD) detection circuit mountable on a substrate of a pluggable component. The circuit comprises a "parallel read" circuit for generating vital product data associated with the pluggable component, a "serial read" circuit for storing and retrieving vital product data associated with the pluggable component, and means for interconnecting the parallel and serial read circuits. The parallel read circuit preferably comprises a parallel array of transistors surface-mounted on the substrate, and the serial read circuit preferably comprises a serial EEPROM having a clock input, a set of address inputs, and a bidirectional data pin. A VPD detection mechanism may disable the parallel VPD circuitry in favor of the serial VPD detection circuitry, or vice versa, or these circuits may be enabled but activated in a mutually exclusive manner.

Abstract: The signal configuration for addressable DRAMs from a system is changed from a signal that actuates a single bank of DRAMs having Y/X row/column addresses actuated by a single RAS, to a signal configuration that provides two RAS signals for two banks of DRAMs having Y-1/X row/column addresses actuated by two RAS signals. This is done by converting the high order address bit from the system to a RAS signal actuated by a system RAS when, and only when, the high order bit is of a given value.

Abstract: A high speed/narrow I/O DRAM device comprises both a data input/output (I/O) port as well as a command port for receiving commands used to control the operations of the DRAM. The command port is defined as input only (i.e., for inputting command data). The present invention comprises multiplexing write data to be written and stored in the DRAM onto the command port with command data packets. The data I/O port can then become dedicated to streaming out seamless data since it no longer needs to flip between input and output data. Even greater bus efficiency can be realized if, during a command packet transfer, data writes to the DRAM are switched back to the data I/O port. With this input port switching protocol, greater bus efficiency and increased memory performance can be realized.

Abstract: A method and logic circuit are provided which method and logic circuit allow both a CBR and hidden refresh to take place on DRAM's populating SIMM's or DIMM's, wherein both a single system RAS and single system CAS are converted to multiple RAS's and multiple CAS's for normal read/write operation on the DRAM's.