Abstract: Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.

Abstract: Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.

Abstract: Methods and structures are presented for protecting flash memory wordlines and memory cells from process-related charging during fabrication. Undoped polysilicon is formed at the ends of doped polysilicon wordlines to create resistors through which process charges are discharged to a doped polysilicon discharge structure coupled with a substrate. The wordlines, resistors, and the discharge structure can be formed as a unitary patterned polysilicon structure, where the wordline and discharge portions are selectively doped to be conductive and the resistor portions are substantially undoped to provide a resistance high enough to allow normal cell operation after fabrication while providing a discharge path for process-related charging during fabrication.

Abstract: Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. The negative gate stress is performed as a block operation by applying a negative gate voltage to gates and connecting active regions and a substrate to ground.