Abstract: A novel synchronous latching scheme is disclosed for use in connection with an EPROM device having a limited number of pins for control signals. A negative edge-triggered d-type master-slave latch having a D-input, and a clock input is provided for generating a program/verify read mode signal. The D-input is coupled to a V.sub.pp /OE control terminal of the EPROM, while the clock input is coupled to a CE/PGM control terminal. During a program interval, while an enabled memory cell is being programmed, and the V.sub.pp control terminal is at a supervoltage, the latch is operable to capture the high level on such control terminal, and provide the high level as an output to define a verify read mode signal. During an immediately-following program verify read interval, the asserted verify mode signal is used to adjust the sense amplifier of the EPROM device so as to provide an increased read margin. During such verify program interval, the V.sub.