Patents by Inventor Mark Winston

Mark Winston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140253733
    Abstract: Tracking objects with a grid of modular security and lighting devices includes triggering, based on event, a first sensor to begin capturing data of an object. In one embodiment, the first sensor is a first camera included in a first modular security and lighting device. The devices within the grid analyze captured sensor data such as first images of the object, and select, based on the analyzing, another sensor such as a second camera to begin capturing data of the object. In one example, the second camera is included in a second modular security and lighting device within the grid of modular security and lighting devices and the first and second modular security and lighting devices are located in geographically distinct locations.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 11, 2014
    Inventors: Glenn Allen Norem, Steven Chien Young Chen, Mark Winston Hershey, Gary Ward Howard
  • Patent number: 5822256
    Abstract: A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: October 13, 1998
    Assignee: Intel Corporation
    Inventors: Mark E. Bauer, Steven Wells, David M. Brown, Johnny Javanifard, Sherif Sweha, Robert N. Hasbun, Gary J. Gallagher, Mamun Rashid, Rodney R. Rozman, Glen Hawk, George Blanchard, Mark Winston, Richard D. Pashley
  • Patent number: 5490264
    Abstract: A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array to produce such a generally-diagonal storage pattern. The arrangement allows the simplest forms of error detection and correction circuitry to be utilized.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: February 6, 1996
    Assignee: Intel Corporation
    Inventors: Steven Wells, Mark Winston
  • Patent number: 5341330
    Abstract: A method for writing data to an entry in a portion of a flash EEPROM memory array during a period in which that portion of the array is being erased and writing is prohibited. The method includes writing the data to a new entry position apart from the portion of the array which is being erased along with a revision number which is greater than the revision number of the original data in the original portion of the array, writing of the busy condition of the original entry to a temporary storage position apart from the portion of the array which is being erased, and invalidating entries listed in the temporary storage position when the erase operation is concluded.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: August 23, 1994
    Assignee: Intel Corporation
    Inventors: Steven E. Wells, Mark Winston, Virgil N. Kynett
  • Patent number: 5222046
    Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.
    Type: Grant
    Filed: October 19, 1990
    Date of Patent: June 22, 1993
    Assignee: Intel Corporation
    Inventors: Jerry A. Kreifels, Alan Baker, George Hoekstra, Virgil N. Kynett, Steven Wells, Mark Winston
  • Patent number: 5053990
    Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
    Type: Grant
    Filed: February 17, 1988
    Date of Patent: October 1, 1991
    Assignee: Intel Corporation
    Inventors: Jerry A. Kreifels, Alan Baker, George Hoekstra, Virgil N. Kynett, Steven Wells, Mark Winston