Abstract: A wearable device includes: at least one compliant region adapted and configured to be placed over a joint of a subject and at least two flexible but less compliant regions coupled to opposite ends of the compliant region. The device provides a wearable robotic device including a wearable and at least one actuator adapted and configured to move the flexible but less compliant regions relative to each other.

Abstract: A wearable device includes: at least one compliant region adapted and configured to be placed over a joint of a subject and at least two flexible but less compliant regions coupled to opposite ends of the compliant region. The device provides a wearable robotic device including a wearable and at least one actuator adapted and configured to move the flexible but less compliant regions relative to each other.

Abstract: One aspect of the invention provides a wearable device including: at least one compliant region adapted and configured to be placed over a joint of a subject and at least two flexible but less compliant regions coupled to opposite ends of the compliant region. Another aspect of the invention provides a wearable robotic device including a wearable device as described herein and at least one actuator adapted and configured to move the flexible but less compliant regions relative to each other.

Abstract: Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.

Abstract: One aspect of the invention provides a wearable device including: at least one compliant region adapted and configured to be placed over a joint of a subject and at least two flexible but less compliant regions coupled to opposite ends of the compliant region. Another aspect of the invention provides a wearable robotic device including a wearable device as described herein and at least one actuator adapted and configured to move the flexible but less compliant regions relative to each other.

Abstract: Disclosed is a monitoring system that includes at least one performance monitor integrated into a semiconductor die. The performance monitor comprises at least one ring oscillator that includes a plurality of stages. Each stage comprises at least one memory device. In one embodiment, the performance monitor may also include a setting circuit that has a burn-in input and an enable input. The setting circuit is capable of setting an input signal of the at least one ring oscillator to a reference voltage level. The performance monitor is configured to produce a ring delay that is characterized by a performance of the at least one memory device. The ring delay may be utilized to scale an operating voltage of the at least one memory device on the semiconductor die.

Abstract: Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.

Abstract: A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. Further, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

Abstract: According to one disclosed embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

Abstract: A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

Abstract: According to one disclosed embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

Abstract: Disclosed is a monitoring system that includes at least one performance monitor integrated into a semiconductor die. The performance monitor comprises at least one ring oscillator that includes a plurality of stages. Each stage comprises at least one memory device. In one embodiment, the performance monitor may also include a setting circuit that has a burn-in input and an enable input. The setting circuit is capable of setting an input signal of the at least one ring oscillator to a reference voltage level. The performance monitor is configured to produce a ring delay that is characterized by a performance of the at least one memory device. The ring delay may be utilized to scale an operating voltage of the at least one memory device on the semiconductor die.

Abstract: A subscriber management system for a communication system having a radio access network coupled to by a gateway node to a packet switched network. The system consolidates three prior art subscriber management system components, a DPI device, a QoS Policy Manager 40, and an Application Manager 28, into a DPI platform. The system also relocates functions to the DPI platform that were previously provided by the gateway node in prior art networks. Specifically, an Accounting Client 34, a Hotlining function 36, and a QoS SFA function 44 are located to the DPI platform. By consolidating network components and relocating functions to the DPI platform, the number of control interfaces in the network can be reduced. Further, network components produced by different vendors may be integrated more easily. A method of implementing hotlining in the system is also provided.

Abstract: A method for authenticating a workflow that has one or more designated steps that require authentication of associated resources, the method comprising: using a reader instrument to read at least one security feature uniquely associated resources involved in the workflow; authenticating the security feature, thereby to authenticate its associated resource, and recording authentication information for each designated workflow step.

Abstract: A subscriber management system for a communication system having a radio access network coupled to by a gateway node to a packet switched network. The system consolidates three prior art subscriber management system components, a DPI device, a QoS Policy Manager 40, and an Application Manager 28, into a DPI platform. The system also relocates functions to the DPI platform that were previously provided by the gateway node in prior art networks. Specifically, an Accounting Client 34, a Hotlining function 36, and a QoS SFA function 44 are located to the DPI platform. By consolidating network components and relocating functions to the DPI platform, the number of control interfaces in the network can be reduced. Further, network components produced by different vendors may be integrated more easily. A method of implementing hotlining in the system is also provided.

Abstract: The present invention provides novel compounds of Formula (I) and Formula (I(a)), or the pharmaceutically acceptable salts thereof; methods for treating neurological disorders and neurodegenerative diseases, particularly pain and migraine, comprising administering a compound of Formula (I) or Formula (I(a)); and processes for preparing compounds of Formula (I) or Formula (I(a)).