Patents by Inventor Mark Y. Liu
Mark Y. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230253499Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: ApplicationFiled: April 13, 2023Publication date: August 10, 2023Inventors: Pratik A. PATEL, Mark Y. LIU, Jami A. WIEDEMER, Paul A. PACKAN
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Patent number: 11664452Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: GrantFiled: October 30, 2020Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
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Patent number: 11387320Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.Type: GrantFiled: December 9, 2019Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Roza Kotlyar, Willy Rachmady, Mark Y. Liu
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Publication number: 20220044971Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: October 19, 2021Publication date: February 10, 2022Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J. WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 11183432Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: April 9, 2020Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
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Publication number: 20210050448Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Inventors: Pratik A. PATEL, Mark Y. LIU, Jami A. WIEDEMER, Paul A. PACKAN
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Patent number: 10872977Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: GrantFiled: April 16, 2019Date of Patent: December 22, 2020Assignee: Intel CorporationInventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
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Publication number: 20200235014Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: April 9, 2020Publication date: July 23, 2020Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J. WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 10651093Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: June 27, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
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Publication number: 20200144362Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.Type: ApplicationFiled: December 9, 2019Publication date: May 7, 2020Applicant: INTEL CORPORATIONInventors: Anand S. MURTHY, Glenn A. GLASS, Tahir GHANI, Ravi PILLARISETTY, Niloy MUKHERJEE, Jack T. KAVALIEROS, Roza KOTLYAR, Willy RACHMADY, Mark Y. LIU
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Publication number: 20190245088Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Inventors: Pratik A. PATEL, Mark Y. LIU, Jami A. WIEDEMER, Paul A. PACKAN
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Patent number: 10304956Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: GrantFiled: December 27, 2013Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
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Publication number: 20190035690Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: ApplicationFiled: June 27, 2018Publication date: January 31, 2019Inventors: Srijit MUKHERJEE, Christopher J. WIEGAND, Tyler J. WEEKS, Mark Y. LIU, Michael L. HATTENDORF
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Patent number: 10170314Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.Type: GrantFiled: August 24, 2016Date of Patent: January 1, 2019Assignee: Intel CorporationInventors: Jacob Jensen, Tahir Ghani, Mark Y. Liu, Harold Kennel, Robert James
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Patent number: 10084087Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: April 17, 2017Date of Patent: September 25, 2018Assignee: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
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Patent number: 10020232Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.Type: GrantFiled: July 27, 2016Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
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Publication number: 20170221724Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Applicant: INTEL CORPORATIONInventors: ANAND S. MURTHY, GLENN A. GLASS, TAHIR GHANI, RAVI PILLARISETTY, NILOY MUKHERJEE, JACK T. KAVALIEROS, ROZA KOTLYAR, WILLY RACHMADY, MARK Y. LIU
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Publication number: 20170222052Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Applicant: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
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Patent number: 9660078Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: November 25, 2015Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 9627384Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.Type: GrantFiled: November 7, 2014Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Roza Kotlyar, Willy Rachmady, Mark Y. Liu