Patents by Inventor Mark Yarch

Mark Yarch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8909862
    Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems. A first device (that is mirroring data from a second device) includes a cache to track out of order write operations prior to writing data from the write operations to memory. A register may be used to track the state of the cache in response to receipt of a special transaction, which may be a posted transaction or snapshot. The first devise transmits an acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Devices may communicate via a peripheral component interconnect express (PCIe) interconnect, and may include a point-to-point or serial link. Various components may be on the same integrated circuit die. An uninterrupted power supply or batteries may supply power in response to a power failure.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Mark A. Yarch, Pankaj Kumar, Hang T. Nguyen
  • Patent number: 8375184
    Abstract: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Pankaj Kumar, Hang T. Nguyen, Mark Yarch, Timothy J. Jehl, John A. Miller
  • Publication number: 20110131373
    Abstract: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Inventors: Pankaj Kumar, Hang T. Nguyen, Mark Yarch, Timothy J. Jehl, John A. Miller
  • Publication number: 20100332877
    Abstract: A system, apparatus, method and article to reduce power consumption are described. The method may include receiving a power management request for a reduced power consumption state from each of a plurality of processors. A power management request for the reduced power consumption state may be sent to a controller to cache data. Each of the plurality of processors may be instructed to enter the reduced power consumption state. An interrupt may be received to return to an active power consumption state. A power management request may be sent to the controller to flush cached data into a memory. Each of the plurality of processors may be instructed to enter the active power consumption state. Other embodiments are described and claimed.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Mark A. Yarch, Hang Nguyen, Sanjeev Jain, Shaun Conrad
  • Publication number: 20100332756
    Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Mark A. Yarch, Pankaj Kumar, Hang T. Nguyen
  • Publication number: 20100306437
    Abstract: A method and apparatus to selectively extend an embedded microprocessor bus through a different external bus are generally presented. In this regard, an apparatus is introduced comprising a first high speed serializer/deserializer (SERDES) bus internal to an integrated circuit device to couple an embedded microprocessor with an embedded component, a second high speed SERDES bus different from the first bus to couple the embedded component with an external interface of the integrated circuit device, and extension circuitry to selectively bypass the embedded component and extend the first bus to function at the external interface over a physical layer of the second bus. Other embodiments are also described and claimed.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Inventors: Matthew W. Heath, Mohan K. Nair, Guadalupe J. Garcia, Bibbin Chacko, Timothy F. Waite, Mark A. Yarch, Hang T. Nguyen, Saiyid Al-Mahmood, Lyonel Renaud, Ganesh Kondapuram, Richard L. Stout
  • Patent number: 6848055
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has two voltage domain regions. The integrated circuit provides for changing the operational voltage of one of the voltage domain regions with respect to the other.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: January 25, 2005
    Assignee: Intel Corporation
    Inventor: Mark A. Yarch
  • Patent number: 6003122
    Abstract: An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first and second alignment stages such that the first alignment stage outputs data aligned in a first dimension according to a second configuration, and the second alignment stage outputs data aligned in a second dimension according to the second configuration.A computer system with a DMA controller with a Memory Write and Invalidate logic circuit is provided. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than or equal to a cacheline size, and the current transfer adders is a multiple of the cacheline size.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: December 14, 1999
    Assignee: Intel Corporation
    Inventors: Mark A. Yarch, Byron R. Gillespie
  • Patent number: 5859990
    Abstract: The present invention provides an alignment logic circuit transferring segments of data from a first storage device to a second storage device. The segments of data are aligned in the first storage device, in a first and second dimension, according to a first configuration. The segments of data are aligned in the second storage device, in the first and second dimension according to a second configuration. The alignment logic circuit includes a first alignment stage, a second alignment stage, and an alignment control logic controls the first alignment stage such that the first alignment stage outputs data aligned in the first dimension according to the second configuration, and the second alignment stage outputs data aligned in the second dimension according to the second configuration.It is also provided a computer system with a DMA controller with a Memory Write and Invalidate logic circuit.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: January 12, 1999
    Assignee: Intel Corporation
    Inventor: Mark A. Yarch
  • Patent number: 5761532
    Abstract: A computer system is provided including a local memory, a local bus coupled to the local memory, a peripheral bus and a direct memory access (DMA) controller. The DMA controller performs DMA transfers of data between the local bus and the peripheral bus. The DMA includes a DMA queue for storing data to be transferred and a bus ownership status circuit for determining bus ownership status of the DMA controller. The DMA controller further includes a local bus interface circuit coupled to the DMA queue and to the status circuit for halting the transfer of data from the local bus to the DMA queue without relinquishing DMA ownership over the local bus when the DMA queue is full and the status circuit indicates that the DMA controller has ownership over both the peripheral bus and the local bus.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: June 2, 1998
    Assignee: Intel Corporation
    Inventors: Mark A. Yarch, Byron R. Gillespie, Marc A. Goldschmidt