Abstract: An integrated circuit includes a memory cell that stores a data bit corresponding to one of a low and a high voltage. A memory element is coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit. At least one write-access port has a write-access switch having an input terminal coupled to a data input line, an output terminal coupled to the data node, and a control terminal coupled to a write control line for switching the write-access switch on or off to provide a write-data bit from the data input line to the write-access port. A preset switch is employed which has a first terminal coupled to one of the data node and the inverse data node, a second terminal coupled to a voltage source sufficient to cause the data node to store a logic-1 data bit when the preset switch is on, and a preset control terminal for switching the preset switch on or off to preset the memory cell before a write operation is coupled to a preset control line.

Abstract: An integrated circuit includes a memory cell that stores a data bit corresponding to one of a low and a high voltage. A memory element is coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit. An access port of the memory cell comprises an access switch having a first terminal coupled to a data line, a second terminal coupled to the data node, and a control terminal coupled to an access control line which provides an access control signal for switching the access switch on or off to selectively couple the data line to the data node. The memory cell has a preset switch having a first terminal coupled to the inverse data node, a second terminal coupled to a logic-0 voltage source, and a preset control terminal coupled to a preset control line which provides a write preset control signal for switching the preset switch on or off to selectively couple the inverse data node to the logic-0 voltage source.