Patents by Inventor Mark Anthony Golez
Mark Anthony Golez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260133716Abstract: Mechanisms, including systems, methods, and media, for tuning a solid-state drive (SSD) are provided, the mechanisms including: providing as an input to a first neural network (NN) current parameter settings (PSs) of the SSD; receiving as an output from the first NN at least one adjustment to the current PSs; based on the at least one adjustment, adjusting the current PSs of the SSD so that the SSD is using adjusted PSs; causing the SSD to execute a workload using the adjusted PSs; determining performance data of the SSD while executing the workload; determining a reward value based on the performance data; and back propagating the first NN based on the reward value.Type: ApplicationFiled: December 23, 2025Publication date: May 14, 2026Inventors: Mark Anthony Golez, Holman Su, John Nolan, Sarvesh Varakabe Gangadhar, Daniel Robert McLeran, Ryan Joseph Norton, Praveen Janga, Lei Chen
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Publication number: 20260104925Abstract: Mechanisms, including systems, methods, and media, for determining a workload type are provided, the method including: receiving a workload; generating a plurality of sets of workload statistics using a hardware processor, wherein each set of workload statistics corresponds to a respective one of a plurality of intervals for the workload; providing the plurality of sets workload statistics to a classifier; receiving an output from the classifier; and based on the output from the classifier, determining a characteristic of the workload. In some embodiments, the characteristic of the workload is that the workload is steady state. In some embodiments, the characteristic of the workload is that the workload is of a given workload type.Type: ApplicationFiled: October 15, 2024Publication date: April 16, 2026Inventors: Mark Anthony Golez, Ravi Motwani, Daniel McLeran
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Publication number: 20260104994Abstract: A method for configuring a memory device includes reading, using a host device, data generated based on memory of a reference memory device, wherein the reference memory device is preconditioned for the performance evaluations, generating a NAND map of the memory based on the reading, wherein the NAND map includes a logical-to-physical address mapping of the memory, and data indicative of invalid physical addresses of the memory, and causing the NAND map to be written to the memory device. In some embodiments, the NAND map includes physical-to-logical address mapping data indicative of valid physical addresses of the logical-to-physical address mapping, and the invalid physical addresses.Type: ApplicationFiled: October 10, 2024Publication date: April 16, 2026Inventors: Niranjan Patankar, Anilmurali Bhaviri, Jonathan Wacker, Mark Anthony Golez, Harsh Singh
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Publication number: 20260099272Abstract: This application is directed to managing memory write operations in a memory system. The memory system includes a controller and non-volatile memory storing data, and the non-volatile memory further includes a first memory block and a second memory block. The memory system successively performs a first batch of foggy programming operations on a plurality of first memory pages located at an end of the first memory block, and opens the second memory block having a plurality of second memory pages located at a start of the second memory block. After the first batch of foggy programming operations, the memory system alternatingly performs a first batch of fine programming operations on the plurality of first memory pages and a second batch of foggy programming operations on the plurality of second memory pages.Type: ApplicationFiled: October 8, 2024Publication date: April 9, 2026Inventors: Justin R. DAYACAP, Sarvesh Varakabe GANGADHAR, David B. CARLTON, Mark Anthony GOLEZ
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Patent number: 12561238Abstract: Mechanisms, including systems, methods, and media, for tuning a solid-state drive (SSD) are provided, the mechanisms including: providing as an input to a first neural network (NN) current parameter settings (PSs) of the SSD; receiving as an output from the first NN at least one adjustment to the current PSs; based on the at least one adjustment, adjusting the current PSs of the SSD so that the SSD is using adjusted PSs; causing the SSD to execute a workload using the adjusted PSs; determining performance data of the SSD while executing the workload; determining a reward value based on the performance data; and back propagating the first NN based on the reward value.Type: GrantFiled: June 24, 2024Date of Patent: February 24, 2026Assignee: SK hynix NAND Product Solutions Corp.Inventors: Mark Anthony Golez, Daniel Robert McLeran, Ryan Joseph Norton, Sarvesh Varakabe Gangadhar, Holman Su, Praveen Janga, Lei Chen
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Publication number: 20260023502Abstract: Mechanisms for identifying sequential workloads in a solid-state drive (SSD) include: receiving a plurality of read commands; and for each of the plurality of read commands: determining that the read command corresponds to a stream of one or more read commands; in response to determining that the read command corresponds to the stream of one or more read commands, incrementing a count of read commands that correspond to the stream; determining that the count meets a threshold count; in response to determining that the count meets the threshold count, determining that the count has met the threshold count for a threshold period of time; and in response to determining that the count has met the threshold count for the threshold period of time, determining that the stream is a sequential workload and taking an action on the stream based on it being determined to be a sequential workload.Type: ApplicationFiled: July 19, 2024Publication date: January 22, 2026Inventors: David J. Pelster, Mohammed Muqsith, Mark Anthony Golez, Teena Sebastian
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Publication number: 20250390430Abstract: Mechanisms, including systems, methods, and media, for tuning a solid-state drive (SSD) are provided, the mechanisms including: providing as an input to a first neural network (NN) current parameter settings (PSs) of the SSD; receiving as an output from the first NN at least one adjustment to the current PSs; based on the at least one adjustment, adjusting the current PSs of the SSD so that the SSD is using adjusted PSs; causing the SSD to execute a workload using the adjusted PSs; determining performance data of the SSD while executing the workload; determining a reward value based on the performance data; and back propagating the first NN based on the reward value.Type: ApplicationFiled: June 24, 2024Publication date: December 25, 2025Inventors: Mark Anthony Golez, Daniel Robert McLeran, Ryan Joseph Norton, Sarvesh Varakabe Gangadhar, Holman Su, Praveen Janga, Lei Chen
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Publication number: 20250348429Abstract: This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.Type: ApplicationFiled: July 22, 2025Publication date: November 13, 2025Inventors: Paul RUBY, David J. Pelster, Mark Anthony Golez, Teena Sebastian
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Publication number: 20250321678Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: ApplicationFiled: June 26, 2025Publication date: October 16, 2025Inventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Patent number: 12366965Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: GrantFiled: September 27, 2023Date of Patent: July 22, 2025Assignee: SK hynix NAND Product Solutions CorporationInventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Patent number: 12367137Abstract: This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.Type: GrantFiled: December 27, 2023Date of Patent: July 22, 2025Assignee: SK Hynix NAND Product Solutions Corp.Inventors: Paul Ruby, David J Pelster, Mark Anthony Golez, Teena Sebastian
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Publication number: 20250217279Abstract: This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.Type: ApplicationFiled: December 27, 2023Publication date: July 3, 2025Inventors: Paul RUBY, David J. PELSTER, Mark Anthony GOLEZ, Teena SEBASTIAN
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Publication number: 20250021231Abstract: This application is directed to dynamic management of memory read request in a memory system of an electronic device. The electronic device identifies a queue of memory access requests to access the memory system. The queue of memory access requests including at least one host read request and a current system read request. The electronic device monitors a workload condition of the memory system based on the queue of memory access requests, and generates at least a first system read request and a second system read request from the current system read request based on the workload condition of the memory system. The queue of memory access requests is updated by inserting the at least one host read request after the first system read request and before the second system read request.Type: ApplicationFiled: October 1, 2024Publication date: January 16, 2025Inventors: Sarvesh Varakabe GANGADHAR, Mark Anthony GOLEZ, Jacky LE
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Patent number: 12118215Abstract: This application is directed to dynamic management of memory read request in a memory system of an electronic device. The electronic device identifies a queue of memory access requests to access the memory system. The queue of memory access requests including at least one host read request and a current system read request. The electronic device monitors a workload condition of the memory system based on the queue of memory access requests, and generates at least a first system read request and a second system read request from the current system read request based on the workload condition of the memory system. The queue of memory access requests is updated by inserting the at least one host read request after the first system read request and before the second system read request.Type: GrantFiled: December 30, 2022Date of Patent: October 15, 2024Assignee: SK Hynix NAND Product Solutions Corp.Inventors: Sarvesh Varakabe Gangadhar, Mark Anthony Golez, Jacky Le
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Publication number: 20240220112Abstract: This application is directed to dynamic management of memory read request in a memory system of an electronic device. The electronic device identifies a queue of memory access requests to access the memory system. The queue of memory access requests including at least one host read request and a current system read request. The electronic device monitors a workload condition of the memory system based on the queue of memory access requests, and generates at least a first system read request and a second system read request from the current system read request based on the workload condition of the memory system. The queue of memory access requests is updated by inserting the at least one host read request after the first system read request and before the second system read request.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Inventors: Sarvesh Varakabe Gangadhar, Mark Anthony Golez, Jacky Le
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Publication number: 20240020013Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Inventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Patent number: 11797188Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: GrantFiled: December 12, 2019Date of Patent: October 24, 2023Assignee: SK hynix NAND Product Solutions Corp.Inventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Publication number: 20220083280Abstract: Read Quality of Service (rQoS) in the solid state drive is improved by reducing latency for host random read workloads. Host read operations for random read workloads are prioritized in the solid state drive over program operations for garbage collection to reduce latency for random read workloads. The program time (tProg) and other associated latencies such as program-suspend-resume overhead, and firmware process overhead to dispatch the program are minimized by minimizing the number of program commands used for garbage collection while the solid state drive is performing read operations for a random read workload for a host read operation, allowing the solid state drive to prioritize host read operations for random read workloads while ensuring that there is no impact to the amount of written data that is on the solid state drive.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Inventors: Holman SU, Mark Anthony GOLEZ, Sarvesh Varakabe GANGADHAR, David J. PELSTER
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Patent number: 10956081Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.Type: GrantFiled: April 18, 2019Date of Patent: March 23, 2021Assignee: INTEL CORPORATIONInventors: David J. Pelster, David B. Carlton, Mark Anthony Golez, Xin Guo, Aliasgar S. Madraswala, Sagar S. Sidhpura, Sagar Upadhyay, Neelesh Vemula, Yogesh B. Wakchaure, Ye Zhang
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Patent number: 10770128Abstract: A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.Type: GrantFiled: September 28, 2018Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Mark Anthony Golez, David J. Pelster, Xin Guo, Paul D. Ruby