Abstract: The present disclosure describes selector pin for a weight stack of a weight exercise machine, and a bolt element for such a selector pin. The bolt element has two first contact points (22.1) positioned along the length of the bolt element (22) on a first side of the bolt element (22), and a second contact point (22.2) between the first contact points on a second side opposite to the first side. The first contact points (22.1) being configured to engage with the weight plate during an exercise, and the second contact point (22.2) being configured to engage with the centre selector shaft. The bolt element may further have a stress sensor configured to determine mechanical stress of the bolt element caused by forces generated by the weight plate and the selector shaft acting on the first and second contact points (22.1; 22.2) of the bolt element (22).

Abstract: The present invention relates to a method and a system of implementing a signal processing facility in a digital transmission system environment. In the invention, the signal between the switching field (GSW) and the interface unit ETS1 is divided into a first (DEOS, DSOE) and second signal (DGO, DSO). The first signal is directed through the signal processing unit and the second signal past it. Either one of the signals is selected and activated depending on the need of the signal processing and the operational status of the signal processing unit; this information the interface unit gets from the control unit.

Abstract: The invention concerns a function taking place in a digital phase lock, when it is desired to exchange a synchronization signal supplied to the phase lock for another synchronization signal. Using a cut-off circuit, the phase difference between a selected reference signal and a signal formed by dividing from an oscillator signal is set with time constant accuracy at the setting value for the phase difference. The method according to the invention, then uses as phase setting value the current value of the phase difference obtained by cut-off connection. Thus, the method according to the invention begins using a reference signal-specific setting value instead of a fixed setting value. Since the setting value is determined adaptively in accordance with the signal of the synchronization source used at each time, no phase transfer will occur during the change.

Abstract: A method and a system for filtering a data stream in a telecom-munications network. The objective of the invention is to provide a filtering mechanism for a data stream whereby the amount of data in the stream is reduced without using compression and with a minimal loss of channel in-formation content. The system comprises two logically different memories. The first memory (201) is used to store channel control information and the second memory (202) to store channel information according to the control channel information stored in the first memory. The fill rate of the first memory is monitored and the content of the second memory is checked by the control unit (200).

Abstract: The present invention relates to a method and a system of implementing a signal processing facility in a digital transmission system environment. In the invention, the signal between the switching field (GSW) and the interface unit ETS1 is divided into a first (DEOS, DSOE) and second signal (DGO, DSO). The first signal is directed through the signal processing unit and the second signal past it. Either one of the signals is selected and activated depending on the need of the signal processing and the operational status of the signal processing unit; this information the interface unit gets from the control unit.

Abstract: The invention concerns a function taking place in a digital phase lock, when it is desired to exchange a synchronization signal supplied to the phase lock for another synchronization signal. Using a cut-off circuit, the phase difference between a selected reference signal and a signal formed by dividing from an oscillator signal is set with time constant accuracy at the setting value for the phase difference. The method according to the invention, then uses as phase setting value the current value of the phase difference obtained by cut-off connection. Thus, the method according to the invention begins using a reference signal-specific setting value instead of a fixed setting value. Since the setting value is determined adaptively in accordance with the signal of the synchronization source used at each time, no phase transfer will occur during the change.

Abstract: The invention relates to a redundant switching arrangement using a first and second switching network (SWF_A, SWF_B) or other switching element. The switching elements are used to carry out switching operations in the same way, so that one of the switching elements serves as an active switching element whose switching operations are utilised, while the other switching element serves as a passive switching element backing up the active switching element. To ensure that any faults occurring in the switching elements in such a redundant switching arrangement are detected as quickly as possible, their operation is monitored by comparing the data of the corresponding output channels of the first and second switching elements, and if such a comparison shows that the data contained in any of the corresponding output channels are not identical, an internal test is carried out for at least one of the switching elements to verify the data of the output channel involved.

Abstract: The invention relates to implementing switching in a switch in a digital telecommunications system. N incoming signals are introduced to the switch, each comprising successive one-bit time slots that form successive frames each comprising K time slots. The contents of the time slots for the incoming signals are stored in a memory at a memory location determined by a write address in such a way that a word having the width of at least one bit is stored at one memory location. One word at a time is read out from the memory, wherefrom the desired bit is selected for the outbound signal from the switch. To optimize the size and power consumption of the switch, the incoming signals are distributed to X multiplexers (A1 . . . Ax), each interleaving the incoming signals thereto into a single serial output signal (IN1 . . .

Abstract: The invention relates to a method and system for automatic compensation of line delay in a clock distribution system which comprises a clock signal generator which supplies a master clock signal through a clock path to a number of decentralized clock signal buffers. According to the invention, the system further comprises a counter, or a similar device, which measures the propagation time of a measuring signal from the corresponding clock signal buffer to the end of the line and back.

Abstract: The present invention relates to a method and device for symmetrizing a clock signal. The leading or trailing edge of each pulse of the clock signal (F.sub.in) to be symmetrized is used for forming the first edge of the pulse of the corresponding symmetrized clock signal (F.sub.out). The pulse ratio of the symmetrized clock signal is measured; and on the basis of the measured pulse ratio, the time constant circuit (R1, C1), determining the location of the second edge of the pulse of the symmetrized clock signal, is adjusted by means of a control loop (R6, C2, A) in such a manner that the second edge of the pulse of the symmetrized clock signal (F.sub.out) settles in a desired position in the symmetrized clock signal. (FIG.

Abstract: A method and circuit in which one of at least two asynchronous constant frequency input clock signals is selected for being used as an output clock signal by use of a separate selection signal for providing redundancy for an asynchronous clock signal.

Abstract: The present invention relates to a method and a system of implementing a signal processing facility in a digital transmission system environment. In the invention, the signal between the switching field (GSW) and the interface unit ETS1 is divided into a first (DEOS, DSOE) and second signal (DGO, DSO). The first signal is directed through the signal processing unit and the second signal past it. Either one of the signals is selected and activated depending on the need of the signal processing and the operational status of the signal processing unit; this information the interface unit gets from the control unit.