Patents by Inventor Marko Chew

Marko Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method to generate an IC layout using simplified manufacturing rule
    Publication number: 20080244480
    Abstract: Some embodiments of the invention provide a system and method where a physical design (“PD”) process can use simplified manufacturing rules to generate an integrated circuit (“IC”) layout. A layout optimization process transforms the PD generated layout to become more manufacturing rule compliant layout using a full set of manufacturing rules.
    Type: Application
    Filed: July 2, 2007
    Publication date: October 2, 2008
    Inventors: Marko Chew, Yue Yang
  • Programmable logic module and architecture for field programmable gate array device
    Patent number: 5698992
    Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: December 16, 1997
    Assignee: Actel Corporation
    Inventors: Khaled A. El Ayat, Gregory W. Bakker, Jung-Cheun Lien, William C. Plants, Sinan Kaptanoglu, Runip Gopisetty, King W. Chan, Marko Chew
  • Programmable logic module and architecture for field programmable gate array device
    Patent number: 5606267
    Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: February 25, 1997
    Assignee: Actel Corporation
    Inventors: Khaled A. El Ayat, Gregory W. Bakker, Jung-Cheun Lien, William C. Plants, Sinan Kaptanoglu, Runip Gopisetty, King W. Chan, Marko Chew
  • Programmable logic module and architecture for field programmable gate array device
    Patent number: 5477165
    Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: December 19, 1995
    Assignee: Actel Corporation
    Inventors: Khaled A. ElAyat, Gregory W. Bakker, Jung-Cheun Lien, William C. Plants, Sinan Kaptanoglu, Runip Gopisetty, King W. Chan, Marko Chew