Abstract: Semiconductor device identification using quantum dot technology. A semiconductor nanocrystal based target is fabricated. A guard ring superjacent the fluorescing surface of the nanocrystal surface is provided to ensure repeatability of spectral mapping and analysis data. A transparent cap on the target may enhance performance. A system for coding a semiconductor device is described. A method is described for fabricating quantum dot targets in a methodology compatible with subsequent semiconductor fabrication process steps.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

Abstract: A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

Abstract: Semiconductor device identification using quantum dot technology. A semiconductor nanocrystal based target is fabricated. A guard ring superjacent the fluorescing surface of the nanocrystal surface is provided to ensure repeatability of spectral mapping and analysis data. A transparent cap on the target may enhance performance. A system for coding a semiconductor device is described. A method is described for fabricating quantum dot targets in a methodology compatible with subsequent semiconductor fabrication process steps.

Abstract: A wafer comprising at least one high Ft HBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.

Abstract: A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

Abstract: A wafer comprising at least one high Ft HBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

Abstract: A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

Abstract: A wafer comprising at least one high Ft HBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

Abstract: Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.

Abstract: A photo-EMF detector including a shield to prevent a portion of the detector from illumination. The shield prevents the generation of unwanted noise-currents, thus increasing the performance of the photo-EMF detector.

Abstract: A photo-EMF detector including a shield to prevent a portion of the detector from illumination. The shield prevents the generation of unwanted noise-currents, thus increasing the performance of the photo-EMF detector.

Abstract: A magnetoresistor is monolithically integrated with an active circuit by growing a thin film magnetoresistor on a semiconductor substrate after the substrate has been doped and annealed for the active devices. The magnetoresistor is grown through a window in a mask, with the mask and magnetoresistor materials selected such that the magnetoresistor is substantially non-adherent to the mask. InSb is preferred for the magnetoresistor, Si.sub.3 N.sub.4 for the mask and GaAs for the substrate. The non-adherence allows the mask to be substantially thinner than the magnetoresistor without impairing the removal of the mask after the magnetoresistor has been established.

Abstract: A magnetoresistor is monolithically integrated with an active circuit by growing a thin film magnetoresistor on a semiconductor substrate after the substrate has been doped and annealed for the active devices. The magnetoresistor is grown through a window in a mask, with the mask and magnetoresistor materials selected such that the magnetoresistor is substantially non-adherent to the mask. InSb is preferred for the magnetoresistor, Si.sub.3 N.sub.4 for the mask and GaAs for the substrate. The non-adherence allows the mask to be substantially thinner than the magnetoresistor without impairing the removal of the mask after the magnetoresistor has been established.

Abstract: A high electron mobility transistor (HEMT) includes a diffusion barrier (22) to prevent gate metal (20) diffusion into the substrate (12) during fabrication and a sacrificial platinum alloy layer (30) forms the Schottky barrier. A method of forming a HEMT includes forming a diffusion barrier of titanium nitride on a platinum layer and applying sufficient heat to cause the platinum layer to alloy with the gallium arsenide layer forming a platinum gallium and platinum arsenide alloy layer and Schottky barrier. Since all platinum is consumed, this method permits precise control of the thickness of the gate layer and eliminates diffusion of the platinum gate layer into the gallium arsenide layer during later processing steps.

Abstract: A field emission device employs an anode in the form of an air bridge spanning the tip of a field emission cathode. The anode is supported only at its opposite ends, leaving the area under the air bridge open. An array of cathode emitters employ a series of parallel, laterally spaced anode air bridges, with each air bridge spanning a line of cathodes. The lateral spacing between the air bridges facilitates both the removal of underlying photo-resist during fabrication, and the establishment of a uniform vacuum if desired. The clearance between the anode and cathode is substantially less than previously obtainable, resulting in a significant reduction in both size and in the anode's operating voltage level. Fabrication of the air bridge anodes can be integrtaed with the remainder of an integrated circuit.