Abstract: In some methods, sampled values based on a reception signal are stored in rows and columns of a memory array. A first 1-dimensional (1D) detector is moved in a first direction over the memory array. The first 1D detector includes a first cell under test and first and second training cells on opposite sides of the first cell under test. The first cell under test and the first and second training cells of the first 1D detector being aligned in the first direction. A second 1D detector is moved over the memory array. The second 1D detector includes a second cell under test and third and fourth training cells on opposite sides of the second cell under test. The second cell under test and the third and fourth training cells of the second 1D detector are aligned in a second direction that is perpendicular to the first direction.

Abstract: A method for a radar system having a plurality of antennas is provided. The method includes processing a plurality of radar signals for determining a distance between the radar system and at least one target and a velocity of the at least one target, thereby forming a plurality of processed radar signals. Each radar signal of the plurality of radar signals is received by an associated antenna of the plurality of antennas. The plurality of processed radar signals are digitally beamformed for at least one beam direction, thereby forming a plurality of beamformed radar signals. The plurality of beamformed radar signals are summed from the plurality of antennas per beam direction.

Abstract: Some aspects of the present disclosure relate to baseband processor for radar. The baseband processor includes a Doppler fast Fourier transform (FFT) circuit having an input and an output. An integration circuit has an input coupled to the output of the Doppler FFT circuit. A target detection circuit has an input coupled to an output of the integration circuit. The Doppler FFT circuit, the integration circuit, and the target detection circuit are each disposed on a silicon substrate, and the target detection circuit is arranged in series with the integration circuit and in series with the target detection circuit.

Abstract: The present disclosure relates to a concept for detecting radar targets. A plurality of first receive signals is received from first antennas of an antenna array. A first combined range-Doppler map is determined by combining range-Doppler maps of each of the first antennas. First confirmable range-Doppler cells of the first combined range-Doppler map are determined which match a predetermined confirmation criterion. A plurality of second receive signals is received from second antennas of the antenna array. A second combined range-Doppler map is determined by combining range-Doppler maps of each of the second antennas. Second confirmable range-Doppler cells of the second combined range-Doppler map are determined which match the predetermined confirmation criterion. The first and second confirmable range-Doppler cells are combined to obtain a set of confirmable range-Doppler cells.

Abstract: A radar system including a direct memory access (DMA). The DMA includes a bus interface including control/status registers and data-in/data-out registers. The DMA also includes potential object queue memory coupled to the bus interface, and a potential object queue logic coupled to the potential object queue memory. The DMA also includes boundary checking circuitry configured to detect whether any portion of a DMA read configuration is greater than a maximum range bin or less than a minimum range bin. The boundary checking circuitry detects whether any portion of the DMA read configuration is greater than a maximum Doppler bin or less than a minimum Doppler bin.

Abstract: A radar system includes a radio frequency (RF) receiver configured to receive radar data at a plurality of receive antennae. A fast Fourier transform (FFT) circuit is coupled to the RF receiver. The FFT circuit is configured to perform a FFT on the radar data to provide a stream of complex values. The stream of complex values includes a plurality of Range-Doppler coordinate pairs that pertain to the plurality of receive antennae. A memory is coupled to the FFT circuit. The memory is configured to store three-dimensional (3D) radar data. A Direct Memory Access circuit (DMA) is coupled to the memory.

Abstract: A baseband processor including a fast Fourier transform (FFT) circuit having an FFT input and an FFT output. A first processing path having a first processing path input and a first processing path output. The first processing path including a memory coupled to the FFT output and the first processing path input via a first bus. A Direct Memory Access (DMA) coupled between the memory and the first processing path output. The DMA coupled to the memory via a second bus. A second processing path arranged in parallel with the first processing path. The second processing path including a detection circuit having a detection circuit input coupled to the FFT output and having a detection circuit output coupled to the DMA.

Abstract: A method of handling radar signals of a radar system having a plurality of antennas is provided. The method may include generating a plurality of time-based radar signals based on a radar signal received by an associated antenna of the plurality of antennas, and transforming each time-based radar signal of the time-based radar signals into radar signals that each comprise a plurality of pairs of a frequency-based-value and an associated intensity value.

Abstract: It is suggested to process radar signals at a first radar unit as follows: (i) receiving the radar signals via at least one receiving antenna; (ii) selecting a portion of the radar signals or of data that is based on the radar signals for further processing; and (iii) conveying a reduced amount of data to a second radar unit, wherein the reduced amount of data is based on the portion of the radar signals or of data that is based on the radar signals.

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

Abstract: A Signal Processing Unit (SPU) having a thresholding circuit configured to detect a peak cell of a radar data cube, and to output an identification of the peak cell and energy values of the peak cell and its adjacent cells; and an interpolation circuit coupled to the thresholding circuit, and configured to determine and transmit from the SPU to a Digital Signal Processor (DSP), a relative position of the peak cell between the adjacent cells based on the energy values.

Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

Abstract: A radar device is provided that is arranged for conducting an interference detection and mitigation based on received and sampled radar signals and storing interference-mitigated data; conducting an FFT on the interference-mitigated data and storing FF-transformed data; conducting a compression on the FF-transformed data into compressed data; and storing the compressed data in a memory. Also, a method for operating such radar device is suggested.

Abstract: A method for the use in a radar system comprises: receiving an RF radar signal; down-converting the received RF radar signal into a base band using a frequency-modulated local oscillator signal including a scanning chirp having a higher bandwidth than a regular chirp bandwidth; generating a digital base band signal based on the down-converted RF radar signal, the digital base band signal including a sequence of samples associated with the scanning chirp; identifying, in the sequence of samples, impaired samples, which are affected by interference; and selecting—based on the position of the impaired samples within the sequence of samples—a sub-band, which has the regular chirp bandwidth, for transmitting chirps of chirp frame used for measurement data acquisition.

Abstract: A processor having a hardware decompressor configured to pad a non-equidistant data set, which is data received at irregular time intervals, with one or more of a predefined value, wherein the data is radar or optical sensor data; and a Fourier transform engine configured to receive the padded non-equidistant data set directly and continuously per data set from the hardware decompressor, and to FFT process the received padded non-equidistant data set.

Abstract: In some methods, sampled values based on a reception signal are stored in rows and columns of a memory array. A first 1-dimensional (1D) detector is moved in a first direction over the memory array. The first 1D detector includes a first cell under test and first and second training cells on opposite sides of the first cell under test. The first cell under test and the first and second training cells of the first 1D detector being aligned in the first direction. A second 1D detector is moved over the memory array. The second 1D detector includes a second cell under test and third and fourth training cells on opposite sides of the second cell under test. The second cell under test and the third and fourth training cells of the second 1D detector are aligned in a second direction that is perpendicular to the first direction.

Abstract: A radar sensor is described herein. In accordance with one example embodiment the radar sensor includes a transmitter for transmitting an RF signal and a receiver configured to receive a respective back-scattered signal from at least one radar target and to provide a corresponding digital radar signal. The radar sensor further includes a processor configured to convert the digital radar signal into the frequency do-main thus providing respective frequency domain data and to compress the frequency domain data. A communication interface is configured to transmit the compressed frequency domain data via a communication link operably coupled to the communication interface. Furthermore, respective and related radar methods and systems are described.

Abstract: A circuit includes a signal processing unit to generate a radar map represented by an array with a first index and a second index, and a peak detection unit to identify potential targets in the radar map. Within the peak detection unit, a first peak detection sub-unit scans the radar map along the first index and stores a first detection bitmap that identifies peaks as a function of the first index, and a second peak detection sub-unit scans the radar map along the second index and outputs a second detection bitmap that identifies peaks as a function of the second index. The first detection bitmap and the second detection bitmap identify the peaks using a single bit. A hardware accelerator processes individual bits of the first detection bitmap and of the second detection bitmap.

Abstract: A radar device is disclosed including an input DMA module, at least one processing module, and an output DMA module. The input DMA module is arranged to access a memory and supply data from the memory to the at least one processing module, wherein each of the processing modules is arranged to be enabled or disabled. The at least one processing module that is enabled is arranged to process at least a portion of the data supplied by the input DMA module, and the output DMA module is arranged to store the data that are processed by the at least one processing module that is enabled in the memory. Also, a method for processing data by a radar device is provided.